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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_watchdog.v] - Diff between revs 136 and 181

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Rev 136 Rev 181
Line 34... Line 34...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 136 $
// $Rev: 181 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2012-03-22 22:14:16 +0100 (Thu, 22 Mar 2012) $
// $LastChangedDate: 2013-02-25 22:24:10 +0100 (Mon, 25 Feb 2013) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`else
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
`endif
`endif
Line 174... Line 174...
parameter [7:0] WDTNMIES_MASK = 8'h40;
parameter [7:0] WDTNMIES_MASK = 8'h40;
`else
`else
parameter [7:0] WDTNMIES_MASK = 8'h00;
parameter [7:0] WDTNMIES_MASK = 8'h00;
`endif
`endif
 
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
  `ifdef WATCHDOG_MUX
  `ifdef WATCHDOG_MUX
parameter [7:0] WDTSSEL_MASK  = 8'h04;
parameter [7:0] WDTSSEL_MASK  = 8'h04;
  `else
  `else
parameter [7:0] WDTSSEL_MASK  = 8'h00;
parameter [7:0] WDTSSEL_MASK  = 8'h00;
  `endif
  `endif
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//=============================================================================
//=============================================================================
// 5)  WATCHDOG TIMER (ASIC IMPLEMENTATION)
// 5)  WATCHDOG TIMER (ASIC IMPLEMENTATION)
//=============================================================================
//=============================================================================
`ifdef ASIC
`ifdef ASIC_CLOCKING
 
 
// Watchdog clock source selection
// Watchdog clock source selection
//---------------------------------
//---------------------------------
wire wdt_clk;
wire wdt_clk;
 
 

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