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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [openMSP430_defines.v] - Diff between revs 155 and 181

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Rev 155 Rev 181
Line 34... Line 34...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 155 $
// $Rev: 181 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2012-10-15 23:35:05 +0200 (Mon, 15 Oct 2012) $
// $LastChangedDate: 2013-02-25 22:24:10 +0100 (Mon, 25 Feb 2013) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
//`define OMSP_NO_INCLUDE
//`define OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`else
`include "openMSP430_undefines.v"
`include "openMSP430_undefines.v"
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//        - Possibility to generate a software PUC reset
//        - Possibility to generate a software PUC reset
//-------------------------------------------------------
//-------------------------------------------------------
`define WATCHDOG
`define WATCHDOG
 
 
 
 
///-------------------------------------------------------
//-------------------------------------------------------
// Include/Exclude Non-Maskable-Interrupt support
// Include/Exclude Non-Maskable-Interrupt support
//-------------------------------------------------------
//-------------------------------------------------------
`define NMI
`define NMI
 
 
 
 
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//-------------------------------------------------------
//-------------------------------------------------------
`define CLOCK_GATING
`define CLOCK_GATING
 
 
 
 
//===============================================================
//===============================================================
 
// ASIC CLOCKING
 
//===============================================================
 
 
 
//-------------------------------------------------------
 
// When uncommented, this define will enable the ASIC
 
// architectural clock gating as well as the advanced low
 
// power modes support (most common).
 
// Comment this out in order to get FPGA-like clocking.
 
//-------------------------------------------------------
 
`define ASIC_CLOCKING
 
 
 
 
 
`ifdef ASIC_CLOCKING
 
//===============================================================
// LFXT CLOCK DOMAIN
// LFXT CLOCK DOMAIN
//===============================================================
//===============================================================
 
 
//-------------------------------------------------------
//-------------------------------------------------------
// When uncommented, this define will enable the lfxt_clk
// When uncommented, this define will enable the lfxt_clk
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// in the following low power modes: LPM4
// in the following low power modes: LPM4
//-------------------------------------------------------
//-------------------------------------------------------
`define OSCOFF_EN
`define OSCOFF_EN
 
 
 
 
 
`endif
`endif
`endif
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//

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