| Line 42... |
Line 42... |
Reset address clarification
|
Reset address clarification
|
|
|
v0.12 | 13/9/11 | Julius Baxter | Addition of extension instructions
|
v0.12 | 13/9/11 | Julius Baxter | Addition of extension instructions
|
l.extbs, l.extbz, l.exths, l.exthz, l.extws and l.extwz. Range exception
|
l.extbs, l.extbz, l.exths, l.exthz, l.extws and l.extwz. Range exception
|
support, overflow bit in supervision register.
|
support, overflow bit in supervision register.
|
|
v0.13 | 27/5/12 | Julius Baxter | Addition of support for delay-slot
|
|
exception indicator bit in supervision register
|
__vend__
|
__vend__
|
////
|
////
|
|
|
Introduction
|
Introduction
|
------------
|
------------
|
| Line 247... |
Line 249... |
((Exception handling)) is transparent to user software and uses the same
|
((Exception handling)) is transparent to user software and uses the same
|
mechanism to handle all types of exceptions. When an exception is taken,
|
mechanism to handle all types of exceptions. When an exception is taken,
|
control is transferred to an exception handler at an offset defined by for
|
control is transferred to an exception handler at an offset defined by for
|
the type of exception encountered. Exceptions are handled in supervisor mode.
|
the type of exception encountered. Exceptions are handled in supervisor mode.
|
|
|
|
Exceptions caused by instructions in a delay slot will set the supervision
|
|
register's DSX bit.
|
|
|
Data Cache
|
Data Cache
|
~~~~~~~~~~
|
~~~~~~~~~~
|
The default configuration of OR1200 data ((cache)) is 8-Kbyte, 1-way
|
The default configuration of OR1200 data ((cache)) is 8-Kbyte, 1-way
|
direct-mapped data cache, which allows rapid core access to data. However
|
direct-mapped data cache, which allows rapid core access to data. However
|
data cache can be configured according to <>.
|
data cache can be configured according to <>.
|
| Line 770... |
Line 775... |
|
|
* Subsequent instructions in program flow are discarded
|
* Subsequent instructions in program flow are discarded
|
* Previous instructions finish and write back their results
|
* Previous instructions finish and write back their results
|
* The address of faulting instruction is saved in EPCR registers and the
|
* The address of faulting instruction is saved in EPCR registers and the
|
machine state is saved to ESR registers
|
machine state is saved to ESR registers
|
|
* If the exception occurred in a delay slot, the DSX bit of the SR is set
|
|
|
[[exceptions_table]]
|
[[exceptions_table]]
|
.List of Implemented ((Exceptions))
|
.List of Implemented ((Exceptions))
|
[width="95%",options="header"]
|
[width="95%",options="header"]
|
|===========================================================
|
|===========================================================
|
| Line 801... |
Line 807... |
| Floating point exception | 0xD00 | FP operation caused flags in FPCSR to
|
| Floating point exception | 0xD00 | FP operation caused flags in FPCSR to
|
become set.
|
become set.
|
| Trap | 0xE00 | Trap instruction was decoded
|
| Trap | 0xE00 | Trap instruction was decoded
|
|===========================================================
|
|===========================================================
|
|
|
The OR1200 exception support does not include support for range exceptions
|
The OR1200 exception support does not include support for fast context
|
or fast context switching.
|
switching.
|
|
|
Data Cache Operation
|
Data Cache Operation
|
~~~~~~~~~~~~~~~~~~~~
|
~~~~~~~~~~~~~~~~~~~~
|
Data Cache Load/Store Access
|
Data Cache Load/Store Access
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
