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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_alu(
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module or1200_alu(
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a, b, mult_mac_result, macrc_op,
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a, b, mult_mac_result, macrc_op,
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alu_op, alu_op2, shrot_op, comp_op,
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alu_op, alu_op2, comp_op,
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cust5_op, cust5_limm,
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cust5_op, cust5_limm,
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result, flagforw, flag_we,
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result, flagforw, flag_we,
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cyforw, cy_we, carry, flag
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cyforw, cy_we, carry, flag
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);
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);
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input [width-1:0] b;
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input [width-1:0] b;
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input [width-1:0] mult_mac_result;
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input [width-1:0] mult_mac_result;
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input macrc_op;
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input macrc_op;
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input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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input [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
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input [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
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input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
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input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
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input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
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input [4:0] cust5_op;
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input [4:0] cust5_op;
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input [5:0] cust5_limm;
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input [5:0] cust5_limm;
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output [width-1:0] result;
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output [width-1:0] result;
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output flagforw;
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output flagforw;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [width-1:0] result;
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reg [width-1:0] result;
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reg [width-1:0] shifted_rotated;
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reg [width-1:0] shifted_rotated;
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reg [width-1:0] extended;
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reg [width-1:0] result_cust5;
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reg [width-1:0] result_cust5;
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reg flagforw;
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reg flagforw;
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reg flagcomp;
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reg flagcomp;
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reg flag_we;
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reg flag_we;
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reg cy_we;
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reg cy_we;
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| Line 146... |
Line 146... |
always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
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always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
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or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
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or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
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`ifdef OR1200_IMPL_ADDC
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`ifdef OR1200_IMPL_ADDC
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or result_csum
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or result_csum
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`endif
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`endif
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`ifdef OR1200_IMPL_ALU_EXT
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or extended
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`endif
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) begin
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) begin
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`ifdef OR1200_CASE_DEFAULT
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`ifdef OR1200_CASE_DEFAULT
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casez (alu_op) // synopsys parallel_case
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casez (alu_op) // synopsys parallel_case
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`else
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`else
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casez (alu_op) // synopsys full_case parallel_case
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casez (alu_op) // synopsys full_case parallel_case
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default: begin // FL1
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default: begin // FL1
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result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;
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result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;
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end
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end
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endcase // casez (alu_op2)
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endcase // casez (alu_op2)
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end // case: `OR1200_ALUOP_FFL1
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end // case: `OR1200_ALUOP_FFL1
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`endif
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`endif // `ifdef OR1200_IMPL_ALU_FFL1
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`ifdef OR1200_IMPL_ALU_CUST5
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`OR1200_ALUOP_CUST5 : begin
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`OR1200_ALUOP_CUST5 : begin
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result = result_cust5;
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result = result_cust5;
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end
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end
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`endif
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`OR1200_ALUOP_SHROT : begin
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`OR1200_ALUOP_SHROT : begin
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result = shifted_rotated;
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result = shifted_rotated;
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end
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end
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`OR1200_ALUOP_ADD : begin
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`OR1200_ALUOP_ADD : begin
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result = result_sum;
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result = result_sum;
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Line 199... |
result = a ^ b;
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result = a ^ b;
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end
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end
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`OR1200_ALUOP_OR : begin
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`OR1200_ALUOP_OR : begin
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result = a | b;
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result = a | b;
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end
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end
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`ifdef OR1200_IMPL_ALU_EXT
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`OR1200_ALUOP_EXTHB : begin
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result = extended;
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end
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`OR1200_ALUOP_EXTW : begin
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result = extended;
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end
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`endif
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`OR1200_ALUOP_MOVHI : begin
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`OR1200_ALUOP_MOVHI : begin
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if (macrc_op) begin
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if (macrc_op) begin
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result = mult_mac_result;
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result = mult_mac_result;
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end
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end
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else begin
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else begin
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Line 240... |
end
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end
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endcase
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endcase
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end
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end
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//
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//
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// l.cust5 custom instructions
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//
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// Examples for move byte, set bit and clear bit
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//
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always @(cust5_op or cust5_limm or a or b) begin
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casez (cust5_op) // synopsys parallel_case
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5'h1 : begin
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casez (cust5_limm[1:0])
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2'h0: result_cust5 = {a[31:8], b[7:0]};
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2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
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2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
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2'h3: result_cust5 = {b[7:0], a[23:0]};
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endcase
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end
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5'h2 :
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result_cust5 = a | (1 << cust5_limm);
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5'h3 :
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result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
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//
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// *** Put here new l.cust5 custom instructions ***
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//
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default: begin
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result_cust5 = a;
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end
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endcase
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end
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//
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// Generate flag and flag write enable
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// Generate flag and flag write enable
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//
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//
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always @(alu_op or result_sum or result_and or flagcomp
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always @(alu_op or result_sum or result_and or flagcomp
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`ifdef OR1200_IMPL_ADDC
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`ifdef OR1200_IMPL_ADDC
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or result_csum
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or result_csum
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| Line 331... |
Line 317... |
end
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end
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//
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//
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// Shifts and rotation
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// Shifts and rotation
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//
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//
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always @(shrot_op or a or b) begin
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always @(alu_op2 or a or b) begin
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case (shrot_op) // synopsys parallel_case
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case (alu_op2) // synopsys parallel_case
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`OR1200_SHROTOP_SLL :
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`OR1200_SHROTOP_SLL :
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shifted_rotated = (a << b[4:0]);
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shifted_rotated = (a << b[4:0]);
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`OR1200_SHROTOP_SRL :
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`OR1200_SHROTOP_SRL :
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shifted_rotated = (a >> b[4:0]);
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shifted_rotated = (a >> b[4:0]);
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`ifdef OR1200_IMPL_ALU_ROTATE
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`ifdef OR1200_IMPL_ALU_ROTATE
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`OR1200_SHROTOP_ROR :
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`OR1200_SHROTOP_ROR :
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shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
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shifted_rotated = (a << (6'd32-{1'b0,b[4:0]})) |
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(a >> b[4:0]);
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`endif
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`endif
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default:
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default:
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shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
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shifted_rotated = ({32{a[31]}} <<
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(6'd32-{1'b0, b[4:0]})) |
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a >> b[4:0];
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endcase
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endcase
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end
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end
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//
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//
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// First type of compare implementation
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// First type of compare implementation
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Line 384... |
flagcomp = 1'b0;
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flagcomp = 1'b0;
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endcase
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endcase
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end
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end
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`endif
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`endif
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`ifdef OR1200_IMPL_ALU_EXT
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always @(alu_op or alu_op2 or a) begin
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casez (alu_op2)
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`OR1200_EXTHBOP_HS : extended = {{16{a[15]}},a[15:0]};
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`OR1200_EXTHBOP_BS : extended = {{24{a[7]}},a[7:0]};
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`OR1200_EXTHBOP_HZ : extended = {16'd0,a[15:0]};
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`OR1200_EXTHBOP_BZ : extended = {24'd0,a[7:0]};
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default: extended = a; // Used for l.extw instructions
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endcase // casez (alu_op2)
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end
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`endif
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//
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// l.cust5 custom instructions
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//
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`ifdef OR1200_IMPL_ALU_CUST5
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// Examples for move byte, set bit and clear bit
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//
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always @(cust5_op or cust5_limm or a or b) begin
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casez (cust5_op) // synopsys parallel_case
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5'h1 : begin
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casez (cust5_limm[1:0])
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2'h0: result_cust5 = {a[31:8], b[7:0]};
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2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
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2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
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2'h3: result_cust5 = {b[7:0], a[23:0]};
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endcase
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end
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5'h2 :
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result_cust5 = a | (1 << cust5_limm);
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5'h3 :
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result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
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//
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// *** Put here new l.cust5 custom instructions ***
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//
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default: begin
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result_cust5 = a;
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end
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endcase
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end // always @ (cust5_op or cust5_limm or a or b)
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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