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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dc_fsm.v] - Diff between revs 258 and 358

Rev 258	Rev 358
Line 357...	Line 357...
assign burst = (state == `OR1200_DCFSM_LOOP2);	assign burst = (state == `OR1200_DCFSM_LOOP2);

`//`	`//`
`// Main DC FSM`	`// Main DC FSM`
`//`	`//`
`always @(posedge clk or posedge rst) begin`	always @(posedge clk or `OR1200_RST_EVENT rst) begin
`if (rst) begin`	if (rst == `OR1200_RST_VALUE) begin
state <= `OR1200_DCFSM_IDLE;	state <= `OR1200_DCFSM_IDLE;
`addr_r <= 32'b0;`	`addr_r <= 32'b0;`
`hitmiss_eval <= 1'b0;`	`hitmiss_eval <= 1'b0;`
`store <= 1'b0;`	`store <= 1'b0;`
`load <= 1'b0;`	`load <= 1'b0;`
Line 553...	Line 553...
state <= `OR1200_DCFSM_IDLE;	state <= `OR1200_DCFSM_IDLE;
`end`	`end`

`endcase // case (state)`	`endcase // case (state)`

`end // always @ (posedge clk or posedge rst)`	end // always @ (posedge clk or `OR1200_RST_EVENT rst)


`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`