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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_freeze.v] - Diff between revs 258 and 358

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Rev 258	Rev 358
Line 137...	Line 137...
`\| (\|waiting_on)) \| du_stall \| mac_stall \| abort_ex;`	`\| (\|waiting_on)) \| du_stall \| mac_stall \| abort_ex;`

`//`	`//`
`// registered flushpipe`	`// registered flushpipe`
`//`	`//`
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`flushpipe_r <= 1'b0;`	`flushpipe_r <= 1'b0;`
`else if (icpu_ack_i \| icpu_err_i)`	`else if (icpu_ack_i \| icpu_err_i)`
`// else if (!if_stall)`	`// else if (!if_stall)`
`flushpipe_r <= flushpipe;`	`flushpipe_r <= flushpipe;`
`else if (!flushpipe)`	`else if (!flushpipe)`
Line 154...	Line 154...
`assign multicycle_freeze = \|multicycle_cnt;`	`assign multicycle_freeze = \|multicycle_cnt;`

`//`	`//`
`// Multicycle counter`	`// Multicycle counter`
`//`	`//`
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`multicycle_cnt <= 2'b00;`	`multicycle_cnt <= 2'b00;`
`else if (\|multicycle_cnt)`	`else if (\|multicycle_cnt)`
`multicycle_cnt <= multicycle_cnt - 2'd1;`	`multicycle_cnt <= multicycle_cnt - 2'd1;`
`else if (\|multicycle & !ex_freeze)`	`else if (\|multicycle & !ex_freeze)`
`multicycle_cnt <= multicycle;`	`multicycle_cnt <= multicycle;`


`//`	`//`
`// Waiting on generation`	`// Waiting on generation`
`//`	`//`
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`waiting_on <= 0;`	`waiting_on <= 0;`
else if ((waiting_on == `OR1200_WAIT_ON_FPU) & fpu_done)	else if ((waiting_on == `OR1200_WAIT_ON_FPU) & fpu_done)
`waiting_on <= 0;`	`waiting_on <= 0;`
else if ((waiting_on == `OR1200_WAIT_ON_MTSPR) & mtspr_done)	else if ((waiting_on == `OR1200_WAIT_ON_MTSPR) & mtspr_done)
`waiting_on <= 0;`	`waiting_on <= 0;`

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_freeze.v] - Diff between revs 258 and 358