| Line 128... |
Line 128... |
reg except_align;
|
reg except_align;
|
|
|
//
|
//
|
// ex_lsu_op
|
// ex_lsu_op
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
ex_lsu_op <= `OR1200_LSUOP_NOP;
|
ex_lsu_op <= `OR1200_LSUOP_NOP;
|
else if (!ex_freeze & id_freeze | flushpipe)
|
else if (!ex_freeze & id_freeze | flushpipe)
|
ex_lsu_op <= `OR1200_LSUOP_NOP;
|
ex_lsu_op <= `OR1200_LSUOP_NOP;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
ex_lsu_op <= id_lsu_op;
|
ex_lsu_op <= id_lsu_op;
|
| Line 143... |
Line 143... |
// Precalculate part of load/store EA in ID stage
|
// Precalculate part of load/store EA in ID stage
|
//
|
//
|
assign id_precalc_sum = id_addrbase[`OR1200_LSUEA_PRECALC-1:0] +
|
assign id_precalc_sum = id_addrbase[`OR1200_LSUEA_PRECALC-1:0] +
|
id_addrofs[`OR1200_LSUEA_PRECALC-1:0];
|
id_addrofs[`OR1200_LSUEA_PRECALC-1:0];
|
|
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
dcpu_adr_r <= {`OR1200_LSUEA_PRECALC{1'b0}};
|
dcpu_adr_r <= {`OR1200_LSUEA_PRECALC{1'b0}};
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
dcpu_adr_r <= id_precalc_sum;
|
dcpu_adr_r <= id_precalc_sum;
|
end
|
end
|
|
|
//
|
//
|
// Generate except_align in ID stage
|
// Generate except_align in ID stage
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
except_align <= 1'b0;
|
except_align <= 1'b0;
|
else if (!ex_freeze & id_freeze | flushpipe)
|
else if (!ex_freeze & id_freeze | flushpipe)
|
except_align <= 1'b0;
|
except_align <= 1'b0;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
except_align <= ((id_lsu_op == `OR1200_LSUOP_SH) |
|
except_align <= ((id_lsu_op == `OR1200_LSUOP_SH) |
|
