URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_mult_mac.v] - Diff between revs 640 and 641

Rev 640	Rev 641
Line 257...	Line 257...
`end`	`end`
`else if (!ex_freeze \| mul_free) begin`	`else if (!ex_freeze \| mul_free) begin`
`mul_free <= 1'b1;`	`mul_free <= 1'b1;`
`end`	`end`

`assign mul_stall = (\|serial_mul_cnt);`	`assign mul_stall = (\|serial_mul_cnt) \| (alu_op_mul & !ex_freeze_r);`

`else	`else

`//`	`//`
`// Instantiation of the multiplier`	`// Instantiation of the multiplier`
Line 409...	Line 409...
`div_quot_r <= {31'b0, x[31:0], 1'b0};`	`div_quot_r <= {31'b0, x[31:0], 1'b0};`
`div_cntr <= 6'b10_0000;`	`div_cntr <= 6'b10_0000;`
`div_free <= 1'b0;`	`div_free <= 1'b0;`
`end`	`end`
`else if (div_free \| !ex_freeze) begin`	`else if (div_free \| !ex_freeze) begin`
`//div_quot_r <= div_quot[63:0];`
`div_free <= 1'b1;`	`div_free <= 1'b1;`
`end`	`end`

`assign div_stall = (\|div_cntr);`	`assign div_stall = (\|div_cntr) \| (!ex_freeze_r & alu_op_div);`


`else // !`ifdef OR1200_DIV_SERIAL	`else // !`ifdef OR1200_DIV_SERIAL

`// Full divider`	`// Full divider`