URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_mult_mac.v] - Diff between revs 643 and 644

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Rev 643	Rev 644
Line 110...	Line 110...
`//`	`//`
`// Internal wires and regs`	`// Internal wires and regs`
`//`	`//`
`reg [width-1:0] result;`	`reg [width-1:0] result;`
`reg ex_freeze_r;`	`reg ex_freeze_r;`
	`wire alu_op_mul;`
	`wire alu_op_smul;`
`ifdef OR1200_MULT_IMPLEMENTED	`ifdef OR1200_MULT_IMPLEMENTED
`reg [2*width-1:0] mul_prod_r;`	`reg [2*width-1:0] mul_prod_r;`
`wire alu_op_smul;`
`wire alu_op_umul;`	`wire alu_op_umul;`
`wire alu_op_mul;`
`ifdef OR1200_MULT_SERIAL	`ifdef OR1200_MULT_SERIAL
`reg [5:0] serial_mul_cnt;`	`reg [5:0] serial_mul_cnt;`
`reg mul_free;`	`reg mul_free;`
`endif	`endif
`else	`else
Line 168...	Line 168...
`//`	`//`
`ifdef OR1200_MULT_IMPLEMENTED	`ifdef OR1200_MULT_IMPLEMENTED
assign alu_op_smul = (alu_op == `OR1200_ALUOP_MUL);	assign alu_op_smul = (alu_op == `OR1200_ALUOP_MUL);
assign alu_op_umul = (alu_op == `OR1200_ALUOP_MULU);	assign alu_op_umul = (alu_op == `OR1200_ALUOP_MULU);
`assign alu_op_mul = alu_op_smul \| alu_op_umul;`	`assign alu_op_mul = alu_op_smul \| alu_op_umul;`
	`else
	`assign alu_op_smul = 0;`
	`assign alu_op_mul = 0;`
`endif	`endif
`ifdef OR1200_MAC_IMPLEMENTED	`ifdef OR1200_MAC_IMPLEMENTED
assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];	assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];	assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];	assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_mult_mac.v] - Diff between revs 643 and 644