OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [ChangeLog] - Diff between revs 118 and 121

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 118 Rev 121
Line 1... Line 1...
 
2010-06-14  Jeremy Bennett 
 
        * configure: Regenerated.
 
        * configure.ac: Version changed to current date.
 
        * cpu/or32/generate.c (gen_eval_operands): Generate macro
 
        REG_PARAM0 to identify register. Corrected undef of SET_PARAM0.
 
        * cpu/or32/insnset.c : Trigger exceptions on use of link
 
        register as destination or non-aligned effective address.
 
        : Trigger exception on use of non-aligned effective address.
 
        * NEWS: Updated with new bugs fixed.
 
 
2010-06-13  Jeremy Bennett 
2010-06-13  Jeremy Bennett 
        * configure: Regenerated.
        * configure: Regenerated.
        * configure.ac: Version changed to current date.
        * configure.ac: Version changed to current date.
        * cpu/or32/generate.c (generate_header): stdint.h included in header.
        * cpu/or32/generate.c (generate_header): stdint.h included in header.
        * cpu/or32/insnset.c : Overflow and carry flags computed and
        * cpu/or32/insnset.c : Overflow and carry flags computed and

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.