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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Diff between revs 112 and 114

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Rev 112 Rev 114
Line 77... Line 77...
    or1k_mstats.byteadd++;
    or1k_mstats.byteadd++;
}
}
INSTRUCTION (l_addc) {
INSTRUCTION (l_addc) {
  orreg_t temp1, temp2, temp3;
  orreg_t temp1, temp2, temp3;
  int8_t temp4;
  int8_t temp4;
 
  int    carry_in = (cpu_state.sprs[SPR_SR] & SPR_SR_CY) == SPR_SR_CY;
 
 
  temp2 = (orreg_t)PARAM2;
  temp2 = (orreg_t)PARAM2;
  temp3 = (orreg_t)PARAM1;
  temp3 = (orreg_t)PARAM1;
  temp1 = temp2 + temp3;
  temp1 = temp2 + temp3;
  if(cpu_state.sprs[SPR_SR] & SPR_SR_CY)
 
    temp1++;
  if(carry_in)
 
    {
 
      temp1++;                          /* Add in the carry bit */
 
    }
 
 
  SET_PARAM0(temp1);
  SET_PARAM0(temp1);
  SET_OV_FLAG_FN (temp1);
 
  if (ARITH_SET_FLAG) {
  /* Set overflow if two negative values gave a positive sum, or if two
    if(!temp1)
     positive values gave a negative sum. Otherwise clear it. There are no
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
     corner cases with the extra bit carried in (unlike the carry flag - see
 
     below). */
 
  if ((((long int) temp2 <  0) &&
 
       ((long int) temp3 <  0) &&
 
       ((long int) temp1 >= 0)) ||
 
      (((long int) temp2 >= 0) &&
 
       ((long int) temp3 >= 0) &&
 
       ((long int) temp1 <  0)))
 
    {
 
      cpu_state.sprs[SPR_SR] |= SPR_SR_OV;
 
    }
    else
    else
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
    {
 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV;
  }
  }
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
 
 
  /* Set the carry flag if (as unsigned values) the result is smaller than
 
     either operand (if it smaller than one, it will be smaller than both, so
 
     we need only test one). If there is a carry in, the test should be less
 
     than or equal, to deal with the 0 + 0xffffffff + c = 0 case (which
 
     generates a carry). */
 
  if ((carry_in && ((uorreg_t) temp1 <= (uorreg_t) temp2)) ||
 
      ((uorreg_t) temp1 < (uorreg_t) temp2))
 
    {
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
 
    }
  else
  else
 
    {
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
 
    }
 
 
 
  /* Trigger a range exception if the overflow flag is set and the SR[OVE] bit
 
     is set. */
 
  if (((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) == SPR_SR_OVE) &&
 
      ((cpu_state.sprs[SPR_SR] & SPR_SR_OV)  == SPR_SR_OV))
 
    {
 
      except_handle (EXCEPT_RANGE, cpu_state.pc);
 
    }
 
 
  temp4 = temp1;
  temp4 = temp1;
  if (temp4 == temp1)
  if (temp4 == temp1)
    or1k_mstats.byteadd++;
    or1k_mstats.byteadd++;
}
}

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