| Line 1... |
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This is ../../or1ksim/doc/or1ksim.info, produced by makeinfo version
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This is ../../doc/or1ksim.info, produced by makeinfo version 4.13 from
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4.13 from ../../or1ksim/doc/or1ksim.texi.
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../../doc/or1ksim.texi.
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INFO-DIR-SECTION Embedded development
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INFO-DIR-SECTION Embedded development
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START-INFO-DIR-ENTRY
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START-INFO-DIR-ENTRY
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* Or1ksim: (or32-uclinux-or1ksim). The OpenRISC 1000 Architectural
|
* Or1ksim: (or32-uclinux-or1ksim). The OpenRISC 1000 Architectural
|
Simulator
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Simulator
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| Line 62... |
Line 62... |
===============
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===============
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|
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Unpack the software and create a _separate_ directory in which to build
|
Unpack the software and create a _separate_ directory in which to build
|
it:
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it:
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tar jxf or1ksim-2010-11-11.tar.bz2
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tar jxf or1ksim-2010-11-25.tar.bz2
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mkdir builddir_or1ksim
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mkdir builddir_or1ksim
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cd builddir_or1ksim
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cd builddir_or1ksim
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File: or1ksim.info, Node: Configuring the Build, Next: Build and Install, Prev: Preparation, Up: Installation
|
File: or1ksim.info, Node: Configuring the Build, Next: Build and Install, Prev: Preparation, Up: Installation
|
| Line 79... |
Line 79... |
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The most significant argument is `--target', which should specify the
|
The most significant argument is `--target', which should specify the
|
OpenRISC 1000 32-bit architecture. If this argument is omitted, it will
|
OpenRISC 1000 32-bit architecture. If this argument is omitted, it will
|
default to OpenRISC 1000 32-bit with a warning
|
default to OpenRISC 1000 32-bit with a warning
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../or1ksim-2010-11-11/configure --target=or32-uclinux ...
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../or1ksim-2010-11-25/configure --target=or32-uclinux ...
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|
|
There are several other options available, many of which are standard
|
There are several other options available, many of which are standard
|
to GNU `configure' scripts. Use `configure --help' to see all the
|
to GNU `configure' scripts. Use `configure --help' to see all the
|
options. The most useful is `--prefix' to specify a directory for
|
options. The most useful is `--prefix' to specify a directory for
|
installation of the tools.
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installation of the tools.
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| Line 520... |
Line 520... |
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The header file `or1ksim.h' contains appropriate declarations of the
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The header file `or1ksim.h' contains appropriate declarations of the
|
functions exported by the Or1ksim library. These are:
|
functions exported by the Or1ksim library. These are:
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|
|
-- `or1ksim.h': int or1ksim_init (int ARGC, char *ARGV, void
|
-- `or1ksim.h': int or1ksim_init (int ARGC, char *ARGV, void
|
*CLASS_PTR,
|
*CLASS_PTR, int (*UPR)(void *CLASS_PTR, unsigned long int
|
int (*UPR)(void *CLASS_PTR, unsigned long int ADDR, unsigned char
|
ADDR, unsigned char MASK[], unsigned char RDATA[], int
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MASK[], unsigned char RDATA[], int DATA_LEN), int (*UPW)(void
|
DATA_LEN), int (*UPW)(void *CLASS_PTR, unsigned long int
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*CLASS_PTR, unsigned long int ADDR, unsigned char MASK[], unsigned
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ADDR, unsigned char MASK[], unsigned char WDATA[], int
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char WDATA[], int DATA_LEN))
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DATA_LEN))
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The initialization function is supplied with a vector of arguments,
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The initialization function is supplied with a vector of arguments,
|
which are interpreted as arguments to the standalone version (see
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which are interpreted as arguments to the standalone version (see
|
*note Standalone Simulator: Standalone Simulator.), a pointer to
|
*note Standalone Simulator: Standalone Simulator.), a pointer to
|
the calling class, CLASS_PTR (since the library may be used from
|
the calling class, CLASS_PTR (since the library may be used from
|
C++) and two up-call functions, one for reads, UPR, and one for
|
C++) and two up-call functions, one for reads, UPR, and one for
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| Line 607... |
Line 606... |
specified in the configuration file.
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specified in the configuration file.
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-- `or1ksim.h': void or1ksim_interrupt (int I)
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-- `or1ksim.h': void or1ksim_interrupt (int I)
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Generate an edge-triggered interrupt on interrupt line I. The
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Generate an edge-triggered interrupt on interrupt line I. The
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interrupt is then immediately cleared automatically. A warning
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interrupt must be cleared separately by clearing the corresponding
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will be generated and the interrupt request ignored if level
|
bit in the PICSR SPR. Until the interrupt is cleared, any further
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sensitive interrupts have been configured with the programmable
|
interrupts on the same line will be ignored with a warning. A
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interrupt controller (*note Interrupt Configuration: Interrupt
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warning will be generated and the interrupt request ignored if
|
Configuration.).
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level sensitive interrupts have been configured with the
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programmable interrupt controller (*note Interrupt Configuration:
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Interrupt Configuration.).
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-- `or1ksim.h': void or1ksim_interrupt_set (int I)
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-- `or1ksim.h': void or1ksim_interrupt_set (int I)
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Assert a level-triggered interrupt on interrupt line I. The
|
Assert a level-triggered interrupt on interrupt line I. The
|
interrupt must be cleared separately by an explicit call to
|
interrupt must be cleared separately by an explicit call to
|
`or1ksim_interrupt_clear'. A warning will be generated, and the
|
`or1ksim_interrupt_clear'. Until the interrupt is cleared, any
|
interrupt request ignored if edge sensitive interrupts have been
|
further setting of interrupts on the same line will be ignored
|
configured with the programmable interrupt controller (*note
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with a warning. A warning will be generated, and the interrupt
|
Interrupt Configuration: Interrupt Configuration.).
|
request ignored if edge sensitive interrupts have been configured
|
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with the programmable interrupt controller (*note Interrupt
|
|
Configuration: Interrupt Configuration.).
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-- `or1ksim.h': void or1ksim_interrupt_clear (int I)
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-- `or1ksim.h': void or1ksim_interrupt_clear (int I)
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Clear a level-triggered interrupt on interrupt line I, which was
|
Clear a level-triggered interrupt on interrupt line I, which was
|
previously asserted by a call to `or1ksim_interrupt_set'. A
|
previously asserted by a call to `or1ksim_interrupt_set'. A
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| Line 640... |
Line 643... |
its own clock, which can be an order of magnitude slower than the
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its own clock, which can be an order of magnitude slower than the
|
main clock, so even a reset (5 JTAG cycles) could take 50
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main clock, so even a reset (5 JTAG cycles) could take 50
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processor clock cycles to complete.
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processor clock cycles to complete.
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-- `or1ksim.h': double or1ksim_jtag_shift_ir (unsigned
|
-- `or1ksim.h': double or1ksim_jtag_shift_ir (unsigned char *JREG, int
|
char *JREG, int NUM_BITS)
|
NUM_BITS)
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Shift the supplied register through the JTAG instruction register.
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Shift the supplied register through the JTAG instruction register.
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Return the (model) time taken for this action. The register is
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Return the (model) time taken for this action. The register is
|
supplied as a byte vector, with the least significant bits in the
|
supplied as a byte vector, with the least significant bits in the
|
least significant byte. If the total number of bits is not an
|
least significant byte. If the total number of bits is not an
|
exact number of bytes, then the odd bits are found in the least
|
exact number of bytes, then the odd bits are found in the least
|
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Line 656... |
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For example a 12-bit register would have bits 0-7 in byte 0 and
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For example a 12-bit register would have bits 0-7 in byte 0 and
|
bits 11-8 in the least significant 4 bits of byte 1.
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bits 11-8 in the least significant 4 bits of byte 1.
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|
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-- `or1ksim.h': double or1ksim_jtag_shift_dr (unsigned
|
-- `or1ksim.h': double or1ksim_jtag_shift_dr (unsigned char *JREG, int
|
char *JREG, int NUM_BITS)
|
NUM_BITS)
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Shift the supplied register through the JTAG data register.
|
Shift the supplied register through the JTAG data register.
|
Return the (model) time taken for this action. The register is
|
Return the (model) time taken for this action. The register is
|
supplied as a byte vector, with the least significant bits in the
|
supplied as a byte vector, with the least significant bits in the
|
least significant byte. If the total number of bits is not an
|
least significant byte. If the total number of bits is not an
|
exact number of bytes, then the odd bits are found in the least
|
exact number of bytes, then the odd bits are found in the least
|
| Line 668... |
Line 669... |
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For example a 12-bit register would have bits 0-7 in byte 0 and
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For example a 12-bit register would have bits 0-7 in byte 0 and
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bits 11-8 in the least significant 4 bits of byte 1.
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bits 11-8 in the least significant 4 bits of byte 1.
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-- `or1ksim.h': int or1ksim_read_mem (unsigned
|
-- `or1ksim.h': int or1ksim_read_mem (unsigned long int ADDR, unsigned
|
long int ADDR, unsigned char *BUF, int LEN)
|
char *BUF, int LEN)
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Read LEN bytes from ADDR, placing the result in BUF. Return LEN
|
Read LEN bytes from ADDR, placing the result in BUF. Return LEN
|
on success and 0 on failure.
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on success and 0 on failure.
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Note: This function was added in Or1ksim 0.5.0.
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Note: This function was added in Or1ksim 0.5.0.
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-- `or1ksim.h': int or1ksim_write_mem (unsigned
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-- `or1ksim.h': int or1ksim_write_mem (unsigned long int ADDR, const
|
long int ADDR, const unsigned char *BUF, int LEN)
|
unsigned char *BUF, int LEN)
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Write LEN bytes to ADDR, taking the data from BUF. Return LEN on
|
Write LEN bytes to ADDR, taking the data from BUF. Return LEN on
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success and 0 on failure.
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success and 0 on failure.
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Note: This function was added in Or1ksim 0.5.0.
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Note: This function was added in Or1ksim 0.5.0.
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-- `or1ksim.h': int or1ksim_read_spr (int SPRNUM, unsigned
|
-- `or1ksim.h': int or1ksim_read_spr (int SPRNUM, unsigned long int
|
long int *SPRVAL_PTR)
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*SPRVAL_PTR)
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Read the SPR specified by SPRNUM, placing the result in
|
Read the SPR specified by SPRNUM, placing the result in
|
SPRVAL_PTR. Return non-zero on success and 0 on failure.
|
SPRVAL_PTR. Return non-zero on success and 0 on failure.
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Note: This function was added in Or1ksim 0.5.0.
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Note: This function was added in Or1ksim 0.5.0.
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-- `or1ksim.h': int or1ksim_write_spr (int SPRNUM, unsigned
|
-- `or1ksim.h': int or1ksim_write_spr (int SPRNUM, unsigned long int
|
long int SPRVA)
|
SPRVA)
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Write SPRVAL to the SPR specified by SPRNUM. Return non-zero on
|
Write SPRVAL to the SPR specified by SPRNUM. Return non-zero on
|
success and 0 on failure.
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success and 0 on failure.
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Note: This function was added in Or1ksim 0.5.0.
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Note: This function was added in Or1ksim 0.5.0.
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-- `or1ksim.h': int or1ksim_read_reg (int REGNUM, unsigned
|
-- `or1ksim.h': int or1ksim_read_reg (int REGNUM, unsigned long int
|
long int *REGVAL_PTR)
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*REGVAL_PTR)
|
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Read the general purpose register specified by REGNUM, placing the
|
Read the general purpose register specified by REGNUM, placing the
|
result in REGVAL_PTR. Return non-zero on success and 0 on failure.
|
result in REGVAL_PTR. Return non-zero on success and 0 on failure.
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|
Note: This function was added in Or1ksim 0.5.0.
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Note: This function was added in Or1ksim 0.5.0.
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-- `or1ksim.h': int or1ksim_write_reg (int REGNUM, unsigned
|
-- `or1ksim.h': int or1ksim_write_reg (int REGNUM, unsigned long int
|
long int REGVA)
|
REGVA)
|
|
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Write REGVAL to the general purpose register specified by REGNUM.
|
Write REGVAL to the general purpose register specified by REGNUM.
|
Return non-zero on success and 0 on failure.
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Return non-zero on success and 0 on failure.
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|
Note: This function was added in Or1ksim 0.5.0.
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Note: This function was added in Or1ksim 0.5.0.
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-- `or1ksim.h': void or1ksim_set_stall_state (int
|
-- `or1ksim.h': void or1ksim_set_stall_state (int STATE)
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STATE)
|
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|
|
Set the processor's state according to STATE (1 = stalled, 0 = not
|
Set the processor's state according to STATE (1 = stalled, 0 = not
|
stalled).
|
stalled).
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Note: This function was added in Or1ksim 0.5.0.
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Note: This function was added in Or1ksim 0.5.0.
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| Line 1547... |
Line 1540... |
|
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`edge_trigger = 0|1'
|
`edge_trigger = 0|1'
|
If 1 (true, the default), the programmable interrupt controller is
|
If 1 (true, the default), the programmable interrupt controller is
|
edge triggered. If 0 (false), it is level triggered.
|
edge triggered. If 0 (false), it is level triggered.
|
|
|
Note: When configured to be edge triggered, interrupts must
|
The library interface (*note Simulator Library: Simulator Library.)
|
be cleared in the PICSR by the processor writing a '0' to the
|
provides different functions for setting the different types of
|
appropriate bit.
|
interrupt, and a function to clear level sensitive interrupts. Edge
|
|
sensitive interrupts must be cleared by clearing the corresponding
|
When configured to be level triggered, the interrupt must be
|
bit in the PICSR SPR.
|
cleared by lowering the peripheral's IRQ line. Writing '0' to
|
|
the PICSR has no effect.
|
Internal functions to set and clear interrupts are also provided
|
|
for peripherals implemented within Or1ksim. *Note Interrupts
|
Peripherals can call the function `report_interrupt' to
|
Internal: Interrupts Internal for more details.
|
signal an interrupt request. When configured for level
|
|
triggered interrupts, the function `clear_interrupt' will
|
`use_nmi = 0|1'
|
clear the appropriate bit in the PICSR. `clear_interrupt' has
|
If 1 (true, the default), interrupt lines 0 and 1 are
|
no effect when Or1ksim is configured for edge triggered
|
non-maskable. In other words the least significant 2 bits of the
|
interrupts - interrupts must be cleared by the processor
|
PICMR SPR are hard-wired to 1. If 0 (false), all interrupt lines
|
writing '0' to the appropriate bit in the PICSR in this case.
|
are treated as equivalent.
|
|
|
|
Note: These are not non-maskable in the true sense that they
|
|
will pre-empt other interrupts. Rather they can never be
|
|
masked out using the PICMR register. It is up the interrupt
|
|
exception handler to give these interrupt lines priority, and
|
|
indeed to decide on the priority order in general.
|
|
|
|
|
|
|
File: or1ksim.info, Node: Power Management Configuration, Next: Branch Prediction Configuration, Prev: Interrupt Configuration, Up: Core OpenRISC Configuration
|
File: or1ksim.info, Node: Power Management Configuration, Next: Branch Prediction Configuration, Prev: Interrupt Configuration, Up: Core OpenRISC Configuration
|
|
|
| Line 2973... |
Line 2972... |
processor is reset by calling `reg_sim_reset', providing a
|
processor is reset by calling `reg_sim_reset', providing a
|
function and pointer to a data structure as arguments. On reset
|
function and pointer to a data structure as arguments. On reset
|
that function will be called with the data stucture pointer as
|
that function will be called with the data stucture pointer as
|
argument.
|
argument.
|
|
|
|
_Interrupts_
|
|
An internal peripheral can model the effect of an interrupt being
|
|
asserted by calling `report_interrupt'. This is used for both edge
|
|
and level sensitive interrupts.
|
|
|
|
The effect is to set the corresponding bit in the PICSR SPR and to
|
|
queue an interrupt exception to take place after the current
|
|
instruction completes execution.
|
|
|
|
Externally, the different interrupts require different mechanisms
|
|
for clearing. Level sensitive interrupts should be cleared by
|
|
deasserting the interrupt line, edge sensitive interrupts by
|
|
clearing the corresponding bit in the PICSR SPR.
|
|
|
|
Internally this amounts to the same thing (clearing the PICSPR
|
|
bit), so a single function is provided, `clear_interrupt'. Note
|
|
however that when level sensitive interrupts are configured, PICSR
|
|
is read only, and can only be cleared by calling
|
|
`clear_interrupt'. Using the two functions provided will ensure
|
|
the peripheral works correctly whichever type of interrupt is used.
|
|
|
|
Note: Until an interrupt is cleared, all subsequent
|
|
interrupts are ignored with a warning.
|
|
|
|
|
|
|
File: or1ksim.info, Node: Internal Debugging, Next: Regression Testing, Prev: Concepts, Up: Code Internals
|
File: or1ksim.info, Node: Internal Debugging, Next: Regression Testing, Prev: Concepts, Up: Code Internals
|
|
|
6.4 Internal Debugging
|
6.4 Internal Debugging
|
| Line 3695... |
Line 3718... |
(line 124)
|
(line 124)
|
* cfgr (CPU configuration): CPU Configuration. (line 47)
|
* cfgr (CPU configuration): CPU Configuration. (line 47)
|
* channel (UART configuration): UART Configuration. (line 29)
|
* channel (UART configuration): UART Configuration. (line 29)
|
* clear breakpoint (Interactive CLI): Interactive Command Line.
|
* clear breakpoint (Interactive CLI): Interactive Command Line.
|
(line 57)
|
(line 57)
|
|
* clear_interrupt: Concepts. (line 20)
|
* clkcycle (simulator configuration): Simulator Behavior. (line 115)
|
* clkcycle (simulator configuration): Simulator Behavior. (line 115)
|
* cm (Interactive CLI): Interactive Command Line.
|
* cm (Interactive CLI): Interactive Command Line.
|
(line 54)
|
(line 54)
|
* command line for Or1ksim standalone use: Standalone Simulator.
|
* command line for Or1ksim standalone use: Standalone Simulator.
|
(line 6)
|
(line 6)
|
| Line 3984... |
Line 4008... |
* instruction profiling utility (Interactive CLI): Interactive Command Line.
|
* instruction profiling utility (Interactive CLI): Interactive Command Line.
|
(line 178)
|
(line 178)
|
* internal debugging: Internal Debugging. (line 6)
|
* internal debugging: Internal Debugging. (line 6)
|
* interrupt controller configuration: Interrupt Configuration.
|
* interrupt controller configuration: Interrupt Configuration.
|
(line 6)
|
(line 6)
|
|
* interrupts: Concepts. (line 20)
|
* irq (ATA/ATAPI configuration): Disc Interface Configuration.
|
* irq (ATA/ATAPI configuration): Disc Interface Configuration.
|
(line 36)
|
(line 36)
|
* irq (DMA configuration): DMA Configuration. (line 34)
|
* irq (DMA configuration): DMA Configuration. (line 34)
|
* irq (GPIO configuration): GPIO Configuration. (line 29)
|
* irq (GPIO configuration): GPIO Configuration. (line 29)
|
* irq (keyboard configuration): Keyboard Configuration.
|
* irq (keyboard configuration): Keyboard Configuration.
|
| Line 4009... |
Line 4034... |
(line 50)
|
(line 50)
|
* log (memory configuration): Memory Configuration.
|
* log (memory configuration): Memory Configuration.
|
(line 156)
|
(line 156)
|
* log_enabled (verification API configuration): Verification API Configuration.
|
* log_enabled (verification API configuration): Verification API Configuration.
|
(line 28)
|
(line 28)
|
* long: Simulator Library. (line 95)
|
* long: Simulator Library. (line 94)
|
* make file for tests: Regression Testing. (line 27)
|
* make file for tests: Regression Testing. (line 27)
|
* mc (memory configuration): Memory Configuration.
|
* mc (memory configuration): Memory Configuration.
|
(line 133)
|
(line 133)
|
* memory configuration: Memory Configuration.
|
* memory configuration: Memory Configuration.
|
(line 6)
|
(line 6)
|
| Line 4054... |
Line 4079... |
* mprof_fn (simulator configuration - deprecated): Simulator Behavior.
|
* mprof_fn (simulator configuration - deprecated): Simulator Behavior.
|
(line 34)
|
(line 34)
|
* mprofile (Interactive CLI): Interactive Command Line.
|
* mprofile (Interactive CLI): Interactive Command Line.
|
(line 173)
|
(line 173)
|
* mprofile (simulator configuration): Simulator Behavior. (line 29)
|
* mprofile (simulator configuration): Simulator Behavior. (line 29)
|
|
* mtspr: Concepts. (line 20)
|
* mwdma (ATA/ATAPI device configuration): Disc Interface Configuration.
|
* mwdma (ATA/ATAPI device configuration): Disc Interface Configuration.
|
(line 132)
|
(line 132)
|
* name (generic peripheral configuration): Generic Peripheral Configuration.
|
* name (generic peripheral configuration): Generic Peripheral Configuration.
|
(line 42)
|
(line 42)
|
* name (memory configuration): Memory Configuration.
|
* name (memory configuration): Memory Configuration.
|
| Line 4067... |
Line 4093... |
* nsets (MMU configuration): Memory Management Configuration.
|
* nsets (MMU configuration): Memory Management Configuration.
|
(line 16)
|
(line 16)
|
* nways (cache configuration): Cache Configuration. (line 22)
|
* nways (cache configuration): Cache Configuration. (line 22)
|
* nways (MMU configuration): Memory Management Configuration.
|
* nways (MMU configuration): Memory Management Configuration.
|
(line 22)
|
(line 22)
|
* or1ksim_get_time_period: Simulator Library. (line 85)
|
* or1ksim_get_time_period: Simulator Library. (line 84)
|
* or1ksim_init: Simulator Library. (line 15)
|
* or1ksim_init: Simulator Library. (line 19)
|
* or1ksim_interrupt: Simulator Library. (line 100)
|
* or1ksim_interrupt: Simulator Library. (line 99)
|
* or1ksim_interrupt_clear: Simulator Library. (line 118)
|
* or1ksim_interrupt_clear: Simulator Library. (line 121)
|
* or1ksim_interrupt_set: Simulator Library. (line 109)
|
* or1ksim_interrupt_set: Simulator Library. (line 110)
|
* or1ksim_is_le: Simulator Library. (line 90)
|
* or1ksim_is_le: Simulator Library. (line 89)
|
* or1ksim_jtag_reset: Simulator Library. (line 127)
|
* or1ksim_jtag_reset: Simulator Library. (line 130)
|
* or1ksim_jtag_shift_dr: Simulator Library. (line 149)
|
* or1ksim_jtag_shift_dr: Simulator Library. (line 152)
|
* or1ksim_jtag_shift_ir: Simulator Library. (line 135)
|
* or1ksim_jtag_shift_ir: Simulator Library. (line 139)
|
* or1ksim_read_mem: Simulator Library. (line 163)
|
* or1ksim_read_mem: Simulator Library. (line 165)
|
* or1ksim_read_reg: Simulator Library. (line 199)
|
* or1ksim_read_reg: Simulator Library. (line 197)
|
* or1ksim_read_spr: Simulator Library. (line 181)
|
* or1ksim_read_spr: Simulator Library. (line 181)
|
* or1ksim_reset_duration: Simulator Library. (line 70)
|
* or1ksim_reset_duration: Simulator Library. (line 69)
|
* or1ksim_run: Simulator Library. (line 59)
|
* or1ksim_run: Simulator Library. (line 58)
|
* or1ksim_set_stall_state: Simulator Library. (line 217)
|
* or1ksim_set_stall_state: Simulator Library. (line 212)
|
* or1ksim_set_time_point: Simulator Library. (line 81)
|
* or1ksim_set_time_point: Simulator Library. (line 80)
|
* or1ksim_write_mem: Simulator Library. (line 172)
|
* or1ksim_write_mem: Simulator Library. (line 173)
|
* or1ksim_write_reg: Simulator Library. (line 208)
|
* or1ksim_write_reg: Simulator Library. (line 205)
|
* or1ksim_write_spr: Simulator Library. (line 190)
|
* or1ksim_write_spr: Simulator Library. (line 189)
|
* output rediretion: Concepts. (line 7)
|
* output rediretion: Concepts. (line 7)
|
* overflow flag setting by instructions: Configuring the Build.
|
* overflow flag setting by instructions: Configuring the Build.
|
(line 133)
|
(line 133)
|
* packet (ATA/ATAPI device configuration): Disc Interface Configuration.
|
* packet (ATA/ATAPI device configuration): Disc Interface Configuration.
|
(line 117)
|
(line 117)
|
| Line 4195... |
Line 4221... |
(line 20)
|
(line 20)
|
* Remote Serial Protocol, --nosrv: Standalone Simulator.
|
* Remote Serial Protocol, --nosrv: Standalone Simulator.
|
(line 52)
|
(line 52)
|
* Remote Serial Protocol, --srv: Standalone Simulator.
|
* Remote Serial Protocol, --srv: Standalone Simulator.
|
(line 60)
|
(line 60)
|
|
* report_interrupt: Concepts. (line 20)
|
* reset (Interactive CLI): Interactive Command Line.
|
* reset (Interactive CLI): Interactive Command Line.
|
(line 63)
|
(line 63)
|
* reset hooks: Concepts. (line 13)
|
* reset hooks: Concepts. (line 13)
|
* reset the simulator (Interactive CLI): Interactive Command Line.
|
* reset the simulator (Interactive CLI): Interactive Command Line.
|
(line 63)
|
(line 63)
|
| Line 4389... |
Line 4416... |
* unstall (Interactive CLI): Interactive Command Line.
|
* unstall (Interactive CLI): Interactive Command Line.
|
(line 78)
|
(line 78)
|
* unstall the processor (Interactive CLI): Interactive Command Line.
|
* unstall the processor (Interactive CLI): Interactive Command Line.
|
(line 78)
|
(line 78)
|
* upr (CPU configuration): CPU Configuration. (line 21)
|
* upr (CPU configuration): CPU Configuration. (line 21)
|
|
* use_nmi (interrupt controller): Interrupt Configuration.
|
|
(line 30)
|
* ustates (cache configuration): Cache Configuration. (line 33)
|
* ustates (cache configuration): Cache Configuration. (line 33)
|
* ustates (MMU configuration): Memory Management Configuration.
|
* ustates (MMU configuration): Memory Management Configuration.
|
(line 41)
|
(line 41)
|
* VAPI configuration: Verification API Configuration.
|
* VAPI configuration: Verification API Configuration.
|
(line 6)
|
(line 6)
|
| Line 4424... |
Line 4453... |
(line 50)
|
(line 50)
|
|
|
|
|
|
|
Tag Table:
|
Tag Table:
|
Node: Top830
|
Node: Top814
|
Node: Installation1240
|
Node: Installation1224
|
Node: Preparation1487
|
Node: Preparation1471
|
Node: Configuring the Build1782
|
Node: Configuring the Build1766
|
Node: Build and Install7926
|
Node: Build and Install7910
|
Node: Known Issues8704
|
Node: Known Issues8688
|
Node: Usage9759
|
Node: Usage9743
|
Node: Standalone Simulator9973
|
Node: Standalone Simulator9957
|
Node: Profiling Utility14537
|
Node: Profiling Utility14521
|
Node: Memory Profiling Utility15447
|
Node: Memory Profiling Utility15431
|
Node: Simulator Library16812
|
Node: Simulator Library16796
|
Node: Configuration26895
|
Node: Configuration27201
|
Node: Configuration File Format27507
|
Node: Configuration File Format27813
|
Node: Configuration File Preprocessing27892
|
Node: Configuration File Preprocessing28198
|
Node: Configuration File Syntax28189
|
Node: Configuration File Syntax28495
|
Node: Simulator Configuration30974
|
Node: Simulator Configuration31280
|
Node: Simulator Behavior31265
|
Node: Simulator Behavior31571
|
Node: Verification API Configuration35846
|
Node: Verification API Configuration36152
|
Node: CUC Configuration37786
|
Node: CUC Configuration38092
|
Node: Core OpenRISC Configuration39778
|
Node: Core OpenRISC Configuration40084
|
Node: CPU Configuration40280
|
Node: CPU Configuration40586
|
Node: Memory Configuration44399
|
Node: Memory Configuration44705
|
Node: Memory Management Configuration51121
|
Node: Memory Management Configuration51427
|
Node: Cache Configuration53498
|
Node: Cache Configuration53804
|
Node: Interrupt Configuration55884
|
Node: Interrupt Configuration56190
|
Node: Power Management Configuration57446
|
Node: Power Management Configuration58023
|
Node: Branch Prediction Configuration58723
|
Node: Branch Prediction Configuration59300
|
Node: Debug Interface Configuration60083
|
Node: Debug Interface Configuration60660
|
Node: Peripheral Configuration62426
|
Node: Peripheral Configuration63003
|
Node: Memory Controller Configuration63052
|
Node: Memory Controller Configuration63629
|
Node: UART Configuration66832
|
Node: UART Configuration67409
|
Node: DMA Configuration70351
|
Node: DMA Configuration70928
|
Node: Ethernet Configuration72218
|
Node: Ethernet Configuration72795
|
Node: GPIO Configuration76300
|
Node: GPIO Configuration76877
|
Node: Display Interface Configuration77933
|
Node: Display Interface Configuration78510
|
Node: Frame Buffer Configuration80242
|
Node: Frame Buffer Configuration80819
|
Node: Keyboard Configuration82106
|
Node: Keyboard Configuration82683
|
Node: Disc Interface Configuration84344
|
Node: Disc Interface Configuration84921
|
Node: Generic Peripheral Configuration89448
|
Node: Generic Peripheral Configuration90025
|
Node: Interactive Command Line91743
|
Node: Interactive Command Line92320
|
Node: Verification API98717
|
Node: Verification API99294
|
Node: Code Internals103147
|
Node: Code Internals103724
|
Node: Coding Conventions103730
|
Node: Coding Conventions104307
|
Node: Global Data Structures108157
|
Node: Global Data Structures108734
|
Node: Concepts110814
|
Node: Concepts111391
|
Ref: Output Redirection110959
|
Ref: Output Redirection111536
|
Node: Internal Debugging111498
|
Ref: Interrupts Internal112074
|
Node: Regression Testing112022
|
Node: Internal Debugging113227
|
Node: GNU Free Documentation License115811
|
Node: Regression Testing113751
|
Node: Index138218
|
Node: GNU Free Documentation License117540
|
|
Node: Index139947
|
|
|
End Tag Table
|
End Tag Table
|
