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* Or1ksim: (or32-uclinux-or1ksim).      The OpenRISC 1000 Architectural

* Or1ksim: (or32-uclinux-or1ksim).      The OpenRISC 1000 Architectural

===============

===============

Unpack the software and create a _separate_ directory in which to build

Unpack the software and create a _separate_ directory in which to build

it:

it:

     mkdir builddir_or1ksim

     mkdir builddir_or1ksim

     cd builddir_or1ksim

     cd builddir_or1ksim

File: or1ksim.info,  Node: Configuring the Build,  Next: Build and Install,  Prev: Preparation,  Up: Installation

File: or1ksim.info,  Node: Configuring the Build,  Next: Build and Install,  Prev: Preparation,  Up: Installation

The most significant argument is `--target', which should specify the

The most significant argument is `--target', which should specify the

OpenRISC 1000 32-bit architecture. If this argument is omitted, it will

OpenRISC 1000 32-bit architecture. If this argument is omitted, it will

default to OpenRISC 1000 32-bit with a warning

default to OpenRISC 1000 32-bit with a warning

There are several other options available, many of which are standard

There are several other options available, many of which are standard

to GNU `configure' scripts. Use `configure --help' to see all the

to GNU `configure' scripts. Use `configure --help' to see all the

options. The most useful is `--prefix' to specify a directory for

options. The most useful is `--prefix' to specify a directory for

installation of the tools.

installation of the tools.

    `--enable-execution=simple'

    `--enable-execution=simple'

          Build the original simple interpreting simulator

          Build the original simple interpreting simulator

    `--enable-execution=complex'

    `--enable-execution=complex'

          Build a more complex interpreting simulator. Experiments

          Build a more complex interpreting simulator. Experiments

    `--enable-execution=dynamic'

    `--enable-execution=dynamic'

     The default is `--enable-execution=complex'.

     The default is `--enable-execution=complex'.

`--enable-ethphy'

`--enable-ethphy'

     `l.srai', `l.sub', `l.xor' and `l.xori'.

     `l.srai', `l.sub', `l.xor' and `l.xori'.

     The default is for this to be disabled.

     The default is for this to be disabled.

          Caution: This appears a very dangerous option, to the extent

          Caution: This appears a very dangerous option, to the extent

          Thus it is impossible to get correct behavior whichever way

          Thus it is impossible to get correct behavior whichever way

          this option is set.

          this option is set.

`--enable-arith-flag'

`--enable-arith-flag'

`--enable-debug'

`--enable-debug'

`--disable-debug'

`--disable-debug'

     This is a feature of the Argtable2 package used to process

     This is a feature of the Argtable2 package used to process

     arguments. If enabled, some debugging features are turned on in

     arguments. If enabled, some debugging features are turned on in

File: or1ksim.info,  Node: Build and Install,  Next: Known Issues,  Prev: Configuring the Build,  Up: Installation

File: or1ksim.info,  Node: Build and Install,  Next: Known Issues,  Prev: Configuring the Build,  Up: Installation

1.3 Building and Installing

1.3 Building and Installing

===========================

===========================

     make all

     make all

     make install

     make install

This will install the three variations of the Or1ksim tool,

This will install the three variations of the Or1ksim tool,

`or32-uclinux-sim', `or32-uclinux-psim' and `or32-uclinux-mpsim', the

`or32-uclinux-sim', `or32-uclinux-psim' and `or32-uclinux-mpsim', the

Or1ksim library, `libsim', the header file, `or1ksim.h' and this

Or1ksim library, `libsim', the header file, `or1ksim.h' and this

File: or1ksim.info,  Node: Known Issues,  Prev: Build and Install,  Up: Installation

File: or1ksim.info,  Node: Known Issues,  Prev: Build and Install,  Up: Installation

1.4 Known Problems and Issues

1.4 Known Problems and Issues

=============================

=============================

   * The Supervision Register Little Endian Enable (LEE) bit is

   * The Supervision Register Little Endian Enable (LEE) bit is

     ignored. Or1ksim can be built for either little endian or big

     ignored. Or1ksim can be built for either little endian or big

     endian use, but that behavior cannot be changed dynamically.

     endian use, but that behavior cannot be changed dynamically.

     original design, and can only be fixed by a complete rewrite. The

     original design, and can only be fixed by a complete rewrite. The

     entire source code uses static global constants liberally!

     entire source code uses static global constants liberally!

   * There is no support for floating point instructions currently in

   * There is no support for floating point instructions currently in

     Or1ksim. However this is a work in progress and should be

     Or1ksim. However this is a work in progress and should be

File: or1ksim.info,  Node: Usage,  Next: Configuration,  Prev: Installation,  Up: Top

File: or1ksim.info,  Node: Usage,  Next: Configuration,  Prev: Installation,  Up: Top

The general form the standalone command is:

The general form the standalone command is:

     or32-uclinux-sim [-vhi] [-f FILE] [--nosrv] [--srv=[N]] [-d STR]

     or32-uclinux-sim [-vhi] [-f FILE] [--nosrv] [--srv=[N]] [-d STR]

                      [--enable-profile] [--enable-mprofile] [FILE]

                      [--enable-profile] [--enable-mprofile] [FILE]

`-v'

`-v'

`--version'

`--version'

     Print out the version and copyright notice for Or1ksim and exit.

     Print out the version and copyright notice for Or1ksim and exit.

`-f FILE'

`-f FILE'

`--file FILE'

`--file FILE'

     Read configuration commands from the specified file, looking first

     Read configuration commands from the specified file, looking first

     in the current directory, and otherwise in the `$HOME/.or1k'

     in the current directory, and otherwise in the `$HOME/.or1k'

     directory. If this argument is not specified, the file `sim.cfg'

     directory. If this argument is not specified, the file `sim.cfg'

`--nosrv'

`--nosrv'

     Do not start up the debug server. This overrides any setting

     Do not start up the debug server. This overrides any setting

     specified in the configuration file. This option may not be

     specified in the configuration file. This option may not be

`--srv'

`--srv'

`--srv=N'

`--srv=N'

     Start up the debug server. If the parameter, N, is specified, use

     Start up the debug server. If the parameter, N, is specified, use

     that as the TCP/IP port for the server, otherwise a random value

     that as the TCP/IP port for the server, otherwise a random value

`-d=CONFIG_STRING'

`-d=CONFIG_STRING'

`--debug-config=CONFIG_STRING'

`--debug-config=CONFIG_STRING'

     Enable selected debug messages in Or1ksim. This parameter is for

     Enable selected debug messages in Or1ksim. This parameter is for

     use by developers only, and is not covered further here. See the

     use by developers only, and is not covered further here. See the

     After starting, drop into the Or1ksim interactive command shell.

     After starting, drop into the Or1ksim interactive command shell.

`--strict-npc'

`--strict-npc'

     In real hardware, setting the next program counter (NPC, SPR 16),

     In real hardware, setting the next program counter (NPC, SPR 16),

     flushes the processor pipeline. The consequence of this is that

     flushes the processor pipeline. The consequence of this is that

     stalled.

     stalled.

     Historically, Or1ksim has always returned the value of the NPC,

     Historically, Or1ksim has always returned the value of the NPC,

     reads of its value will return 0 until the processor is unstalled.

     reads of its value will return 0 until the processor is unstalled.

     This is not currently the default behavior, since tools such as

     This is not currently the default behavior, since tools such as

     GDB have been implemented assuming the historic Or1ksim behavior.

     GDB have been implemented assuming the historic Or1ksim behavior.

     However at some time in the future it will become the default.

     However at some time in the future it will become the default.

File: or1ksim.info,  Node: Profiling Utility,  Next: Memory Profiling Utility,  Prev: Standalone Simulator,  Up: Usage

File: or1ksim.info,  Node: Profiling Utility,  Next: Memory Profiling Utility,  Prev: Standalone Simulator,  Up: Usage

2.2 Profiling Utility

2.2 Profiling Utility

=====================

=====================

     or32-uclinux-profile [-vhcq] [-g=FILE]

     or32-uclinux-profile [-vhcq] [-g=FILE]

`-v'

`-v'

`--version'

`--version'

     Print out the version and copyright notice for the Or1ksim

     Print out the version and copyright notice for the Or1ksim

     profiling utility and exit.

     profiling utility and exit.

be invoked as a standalone command, or from the Or1ksim CLI. The

be invoked as a standalone command, or from the Or1ksim CLI. The

general form the standalone command is:

general form the standalone command is:

     or32-uclinux-mprofile  [-vh] [-m=M] [-g=N] [-f=FILE] FROM TO

     or32-uclinux-mprofile  [-vh] [-m=M] [-g=N] [-f=FILE] FROM TO

`-v'

`-v'

`--version'

`--version'

     Print out the version and copyright notice for the Or1ksim memory

     Print out the version and copyright notice for the Or1ksim memory

     profiling utility and exit.

     profiling utility and exit.

     *Note Configuration: Configuration, for detailed information on

     *Note Configuration: Configuration, for detailed information on

     configuring Or1ksim and the format of the configuration file.

     configuring Or1ksim and the format of the configuration file.

     UPW is called for any write to an address external to the model

     UPW is called for any write to an address external to the model

     MASK indicates which bytes in the word are to be written or read.

     MASK indicates which bytes in the word are to be written or read.

     Bytes to be read/written should have 0xff set in MASK. Otherwise

     Bytes to be read/written should have 0xff set in MASK. Otherwise

     the byte should be zero.

     the byte should be zero.

     Return 1 (logical true) if the Or1ksim simulation is

     Return 1 (logical true) if the Or1ksim simulation is

     little-endian, 0 otherwise.

     little-endian, 0 otherwise.

 -- `or1ksim.h': unsigned long int or1ksim_clock_rate ()

 -- `or1ksim.h': unsigned long int or1ksim_clock_rate ()

 -- `or1ksim.h': void or1ksim_interrupt (int I)

 -- `or1ksim.h': void or1ksim_interrupt (int I)

     Generate an edge-triggered interrupt on interrupt line I. The

     Generate an edge-triggered interrupt on interrupt line I. The

     interrupt is then immediately cleared automatically. A warning

     interrupt is then immediately cleared automatically. A warning

All optional parts of the functionality are always described by

All optional parts of the functionality are always described by

sections including a `enabled' parameter, which can be set to 0 to

sections including a `enabled' parameter, which can be set to 0 to

ensure that functionality is explicitly omitted.

ensure that functionality is explicitly omitted.

Even if a section is disabled, all its parameters will be read and

Even if a section is disabled, all its parameters will be read and

Command Line.).

Command Line.).

     Tip: It generally clearer to have sections describing _all_

     Tip: It generally clearer to have sections describing _all_

     components, with omitted functionality explicitly indicated by

     components, with omitted functionality explicitly indicated by

     setting the `enabled' parameter to 0

     setting the `enabled' parameter to 0

     If 1 (true), print extra messages. Default 0.

     If 1 (true), print extra messages. Default 0.

`debug = 0-9'

`debug = 0-9'

     0 means no debug messages. 1-9 means produce debug messages. The

     0 means no debug messages. 1-9 means produce debug messages. The

     higher the value the greater the number of messages. Default 0.

     higher the value the greater the number of messages. Default 0.

`profile = 0|1'

`profile = 0|1'

     If 1 (true) generate a profiling file using the file specified in

     If 1 (true) generate a profiling file using the file specified in

     the `prof_file' parameter or otherwise `sim.profile'. Default 0.

     the `prof_file' parameter or otherwise `sim.profile'. Default 0.

`prof_file = ``FILENAME'''

`prof_file = ``FILENAME'''

`mprofile = 0|1'

`mprofile = 0|1'

     If 1 (true) generate a memory profiling file using the file

     If 1 (true) generate a memory profiling file using the file

     specified in the `mprof_file' parameter or otherwise

     specified in the `mprof_file' parameter or otherwise

     `sim.mprofile'. Default 0.

     `sim.mprofile'. Default 0.

          Note: If this execution flow tracking is enabled, then

          Note: If this execution flow tracking is enabled, then

          `dependstats' must be enabled in the CPU configuration

          `dependstats' must be enabled in the CPU configuration

          section (*note CPU Configuration: CPU Configuration.).

          section (*note CPU Configuration: CPU Configuration.).

`exe_log = 0|1'

`exe_log = 0|1'

          Note: Setting this parameter seriously degrades performance.

          Note: Setting this parameter seriously degrades performance.

`exe_log_type = default|hardware|simple|software'

`exe_log_type = default|hardware|simple|software'

     Type of execution log to produce.

     Type of execution log to produce.

`exe_log_start = VALUE'

`exe_log_start = VALUE'

     Address of the first instruction to start logging. Default 0.

     Address of the first instruction to start logging. Default 0.

`exe_log_end = VALUE'

`exe_log_end = VALUE'

`exe_log_marker = VALUE'

`exe_log_marker = VALUE'

     Specifies the number of instructions between printing horizontal

     Specifies the number of instructions between printing horizontal

     markers. Default is to produce no markers.

     markers. Default is to produce no markers.

`enable_bursts = 0 | 1'

`enable_bursts = 0 | 1'

     If 1 (true), bursts are detected. If 0 (the default), bursts are

     If 1 (true), bursts are detected. If 0 (the default), bursts are

     not detected.

     not detected.

`no_multicycle = 0 | 1'

`no_multicycle = 0 | 1'

`timings_file = "FILENAME"'

`timings_file = "FILENAME"'

     FILENAME specifies a file containing timing information. The

     FILENAME specifies a file containing timing information. The

     default value is `"virtex.tim"'. For backwards compatibility, the

     default value is `"virtex.tim"'. For backwards compatibility, the

     alternative name `timings_fn' is supported for this parameter, but

     alternative name `timings_fn' is supported for this parameter, but

          Caution: The code for this does not appear to be complete or

          Caution: The code for this does not appear to be complete or

          well tested, so users are advised not to use this option.

          well tested, so users are advised not to use this option.

`hazards = 0|1'

`hazards = 0|1'

     In the current simulator, the only functional effect is to cause

     In the current simulator, the only functional effect is to cause

     logging of hazard waiting information if the CPU is superscalar.

     logging of hazard waiting information if the CPU is superscalar.

     However nowhere in the simulator is this data actually computed,

     However nowhere in the simulator is this data actually computed,

     so the net result is probably to have no effect.

     so the net result is probably to have no effect.

          Caution: The code for this does not appear to be complete or

          Caution: The code for this does not appear to be complete or

          well tested, so users are advised not to use this option.

          well tested, so users are advised not to use this option.

`dependstats = 0|1'

`dependstats = 0|1'

     If these values are calculated, the depencies can be displayed

     If these values are calculated, the depencies can be displayed

     using the simulator's `stat' command.

     using the simulator's `stat' command.

          Note: This field must be enabled, if execution execution flow

          Note: This field must be enabled, if execution execution flow

          Behavior.).

          Behavior.).

`sbuf_len = VALUE'

`sbuf_len = VALUE'

     The length of the store buffer is set to VALUE, which must be no

     The length of the store buffer is set to VALUE, which must be no

     greater than 256. Larger values will be truncated to 256 with a

     greater than 256. Larger values will be truncated to 256 with a

     When the store buffer is active, stores are accumulated and

     When the store buffer is active, stores are accumulated and

     committed when I/O is idle.

     committed when I/O is idle.

File: or1ksim.info,  Node: Memory Configuration,  Next: Memory Management Configuration,  Prev: CPU Configuration,  Up: Core OpenRISC Configuration

File: or1ksim.info,  Node: Memory Configuration,  Next: Memory Management Configuration,  Prev: CPU Configuration,  Up: Core OpenRISC Configuration

3.3.2 Memory Configuration

3.3.2 Memory Configuration

--------------------------

--------------------------

following parameters may be specified.

following parameters may be specified.

`type=random|pattern|unknown|zero'

`type=random|pattern|unknown|zero'

     Specifies the values to which memory should be initialized. The

     Specifies the values to which memory should be initialized. The

     default value is `unknown'.

     default value is `unknown'.

     Set the base address of the memory to VALUE. It should be aligned

     Set the base address of the memory to VALUE. It should be aligned

     to a multiple of the memory size rounded up to the nearest 2^n.

     to a multiple of the memory size rounded up to the nearest 2^n.

     The default value is 0.

     The default value is 0.

`size = VALUE'

`size = VALUE'

          Note: When allocating memory, the simulator will allocate the

          Note: When allocating memory, the simulator will allocate the

          nearest 2^n bytes greater than or equal to VALUE, and will not

          nearest 2^n bytes greater than or equal to VALUE, and will not

          notice memory misses in any part of the memory between VALUE

          notice memory misses in any part of the memory between VALUE

          and the amount allocated.

          and the amount allocated.

     which do not fit these criteria are ignored with a warning. The

     which do not fit these criteria are ignored with a warning. The

     default value is 1.

     default value is 1.

`nways = VALUE'

`nways = VALUE'

     Sets the number of data or instruction (as appropriate) TLB ways to

     Sets the number of data or instruction (as appropriate) TLB ways to

`pagesize = VALUE'

`pagesize = VALUE'

     The data or instruction (as appropriate) MMU page size is set to

     The data or instruction (as appropriate) MMU page size is set to

`entrysize = VALUE'

`entrysize = VALUE'

     The data or instruction (as appropriate) MMU entry size is set to

     The data or instruction (as appropriate) MMU entry size is set to

          Note: Or1ksim does not appear to use the `entrysize' parameter

          Note: Or1ksim does not appear to use the `entrysize' parameter

          in its simulation of the MMUs. Thus setting this value does

          in its simulation of the MMUs. Thus setting this value does

          not seem to matter.

          not seem to matter.

`load_hitdelay = VALUE'

`load_hitdelay = VALUE'

     _Data cache only_. Set the number of cycles a data load cache hit

     _Data cache only_. Set the number of cycles a data load cache hit

     costs. Default value 2.

     costs. Default value 2.

`load_missdelay = VALUE'

`load_missdelay = VALUE'

`store_hitdelay = VALUE'

`store_hitdelay = VALUE'

     _Data cache only_. Set the number of cycles a data store cache hit

     _Data cache only_. Set the number of cycles a data store cache hit

     costs. Default value 0.

     costs. Default value 0.

`section pic'. This section may appear at most once--Or1ksim has no

`section pic'. This section may appear at most once--Or1ksim has no

mechanism for handling multiple interrupt controllers. The following

mechanism for handling multiple interrupt controllers. The following

parameters may be specified.

parameters may be specified.

`enabled = 0|1'

`enabled = 0|1'

`edge_trigger = 0|1'

`edge_trigger = 0|1'

     If 1 (true, the default), the programmable interrupt controller is

     If 1 (true, the default), the programmable interrupt controller is

     edge triggered. If 0 (false), it is level triggered.

     edge triggered. If 0 (false), it is level triggered.

Power management configuration is described in `section pm'. This

Power management configuration is described in `section pm'. This

section may appear at most once. The following parameter may be

section may appear at most once. The following parameter may be

specified.

specified.

`enabled = 0|1'

`enabled = 0|1'

File: or1ksim.info,  Node: Branch Prediction Configuration,  Next: Debug Interface Configuration,  Prev: Power Management Configuration,  Up: Core OpenRISC Configuration

File: or1ksim.info,  Node: Branch Prediction Configuration,  Next: Debug Interface Configuration,  Prev: Power Management Configuration,  Up: Core OpenRISC Configuration

3.3.7 Branch Prediction Configuration

3.3.7 Branch Prediction Configuration

-------------------------------------

-------------------------------------

From examining the code base, it seems the branch prediction function

From examining the code base, it seems the branch prediction function

Branch prediction configuration is described in `section bpb'. This

Branch prediction configuration is described in `section bpb'. This

section may appear at most once. The following parameters may be

section may appear at most once. The following parameters may be

specified.

specified.

     If 1 (true), use forward prediction for the `l.bf' instruction. If

     If 1 (true), use forward prediction for the `l.bf' instruction. If

     0 (the default), do not use forward prediction for this

     0 (the default), do not use forward prediction for this

     instruction.

     instruction.

`sbp_bnf_fwd = 0|1'

`sbp_bnf_fwd = 0|1'

     instruction.

     instruction.

`hitdelay = VALUE'

`hitdelay = VALUE'

     Set the number of cycles a branch prediction hit costs. Default

     Set the number of cycles a branch prediction hit costs. Default

     value 0.

     value 0.

     For more detailed information on the interface to the GNU Debugger

     For more detailed information on the interface to the GNU Debugger

     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger

     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger

     Practical Experience with the OpenRISC 1000 Architecture', by

     Practical Experience with the OpenRISC 1000 Architecture', by

     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').

     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').

`rsp_port = VALUE'

`rsp_port = VALUE'

     VALUE specifies the port to be used for the GDB "Remote Serial

     VALUE specifies the port to be used for the GDB "Remote Serial

     Protocol" interface to the GNU Debugger (GDB). Default value

     Protocol" interface to the GNU Debugger (GDB). Default value

     51000. If the value 0 is specified, Or1ksim will instead look for

     51000. If the value 0 is specified, Or1ksim will instead look for

     a TCP/IP service named `or1ksim-rsp'.

     a TCP/IP service named `or1ksim-rsp'.

          Tip: There is no registered port for Or1ksim "Remote Serial

          Tip: There is no registered port for Or1ksim "Remote Serial

`gdb_enabled = 0|1'

`gdb_enabled = 0|1'

     If 1 (true), the OpenRISC Remote JTAG protocol server is started,

     If 1 (true), the OpenRISC Remote JTAG protocol server is started,

     provding an interface to an external GNU debugger, using the port

     provding an interface to an external GNU debugger, using the port

     specified in the `server_port' field (see below), or the `or1ksim'

     specified in the `server_port' field (see below), or the `or1ksim'

     For more detailed information on the interface to the GNU Debugger

     For more detailed information on the interface to the GNU Debugger

     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger

     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger

     Practical Experience with the OpenRISC 1000 Architecture', by

     Practical Experience with the OpenRISC 1000 Architecture', by

     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').

     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').

          OpenRISC, and remains only for backward compatibility. New

          OpenRISC, and remains only for backward compatibility. New

          users should adopt the standard GDB "Remote Serial Protocol"

          users should adopt the standard GDB "Remote Serial Protocol"

          interface (see `rsp_enabled' above) providing access to a

          interface (see `rsp_enabled' above) providing access to a

          wider range of GDB functionality.

          wider range of GDB functionality.

          Serial Protocol" interface is enabled.

          Serial Protocol" interface is enabled.

`server_port = VALUE'

`server_port = VALUE'

     VALUE specifies the port to be used for the OpenRISC Rmote JTAG

     VALUE specifies the port to be used for the OpenRISC Rmote JTAG

          Tip: There is no registered port for Or1ksim Remote JTAG

          Tip: There is no registered port for Or1ksim Remote JTAG

          Interface or service `or1ksim'. Good practice suggests users

          Interface or service `or1ksim'. Good practice suggests users

          should adopt port values in the "Dynamic" or "Private" port

          should adopt port values in the "Dynamic" or "Private" port

          range, i.e. 49152-65535.

          range, i.e. 49152-65535.

-------------------------------------

-------------------------------------

The memory controller used in Or1ksim is the component implemented at

The memory controller used in Or1ksim is the component implemented at

OpenCores, and found in the top level CVS directory, `mem_ctrl'. It is

OpenCores, and found in the top level CVS directory, `mem_ctrl'. It is

described in the document `Memory Controller IP Core' by Rudolf

described in the document `Memory Controller IP Core' by Rudolf

The memory controller configuration is described in `section mc'. This

The memory controller configuration is described in `section mc'. This

section may appear multiple times, specifying multiple memory

section may appear multiple times, specifying multiple memory

controllers. The following parameters may be specified.

controllers. The following parameters may be specified.

`enabled = 0|1'

`enabled = 0|1'

          Note: The memory controller can effectively also be disabled

          Note: The memory controller can effectively also be disabled

          by setting an appropriate power on control register value

          by setting an appropriate power on control register value

          (see below). However this should only be used if it is

          (see below). However this should only be used if it is

          desired to specifically model this behavior of the memory

          desired to specifically model this behavior of the memory

          required).

          required).

    `channel="xterm:ARGS"'

    `channel="xterm:ARGS"'

          Create an xterm on startup, write UART Tx traffic to the

          Create an xterm on startup, write UART Tx traffic to the

          xterm and take Rx traffic from the keyboard when the xterm

          xterm and take Rx traffic from the keyboard when the xterm

    `channel="tcp:VALUE"'

    `channel="tcp:VALUE"'

          Open the TCP/IP port specified by VALUE and read and write

          Open the TCP/IP port specified by VALUE and read and write

          UART traffic from and to it.

          UART traffic from and to it.

-----------------------

-----------------------

The DMA controller used in Or1ksim is the component implemented at

The DMA controller used in Or1ksim is the component implemented at

OpenCores, and found in the top level CVS directory, `wb_dma'. It is

OpenCores, and found in the top level CVS directory, `wb_dma'. It is

described in the document `Wishbone DMA/Bridge IP Core' by Rudolf

described in the document `Wishbone DMA/Bridge IP Core' by Rudolf

DMA configuration is described in `section dma'. This section may

DMA configuration is described in `section dma'. This section may

appear multiple times, specifying multiple DMA controllers. The

appear multiple times, specifying multiple DMA controllers. The

following parameters may be specified.

following parameters may be specified.

`enabled = 0|1'

`enabled = 0|1'

`baseaddr = VALUE'

`baseaddr = VALUE'

     Set the base address of the DMA's memory mapped registers to

     Set the base address of the DMA's memory mapped registers to

     VALUE. The default is 0, which is probably not a sensible value.

     VALUE. The default is 0, which is probably not a sensible value.

     The DMA controller has a 10 bit address bus, with a total of 253

     The DMA controller has a 10 bit address bus, with a total of 253

     32-bit registers. The first 5 registers at addresses 0x000 through

     32-bit registers. The first 5 registers at addresses 0x000 through

     channels available. Addresses 0x014 through 0x01c are not used.

     channels available. Addresses 0x014 through 0x01c are not used.

`irq = VALUE'

`irq = VALUE'

     Use VALUE as the IRQ number of this DMA controller. Default value

     Use VALUE as the IRQ number of this DMA controller. Default value

     0.

     0.

The Ethernet MAC used in Or1ksim is the component implemented at

The Ethernet MAC used in Or1ksim is the component implemented at

OpenCores, and found in the top level CVS directory, `ethernet'. It

OpenCores, and found in the top level CVS directory, `ethernet'. It

also forms part of the OpenRISC SoC, ORPSoC. It is described in the

also forms part of the OpenRISC SoC, ORPSoC. It is described in the

document `Ethernet IP Core Specification' by Igor Mohor, which can be

document `Ethernet IP Core Specification' by Igor Mohor, which can be

`enabled = 0|1'

`enabled = 0|1'

`baseaddr = VALUE'

`baseaddr = VALUE'

     Set the base address of the MAC's memory mapped registers to

     Set the base address of the MAC's memory mapped registers to

     VALUE. The default is 0, which is probably not a sensible value.

     VALUE. The default is 0, which is probably not a sensible value.

     The Ethernet MAC has a 7-bit address bus, with a total of 21

     The Ethernet MAC has a 7-bit address bus, with a total of 21

     32-bit registers. Addresses 0x54 through 0x7c are not used.

     32-bit registers. Addresses 0x54 through 0x7c are not used.

          Note: The Ethernet specification describes a Tx control

          Note: The Ethernet specification describes a Tx control

`dma = VALUE'

`dma = VALUE'

     VALUE specifies the DMA controller with which this Ethernet is

     VALUE specifies the DMA controller with which this Ethernet is

     associated. The default value is 0.

     associated. The default value is 0.

`irq = VALUE'

`irq = VALUE'

     Use VALUE as the IRQ number of this Ethernet MAC. Default value 0.

     Use VALUE as the IRQ number of this Ethernet MAC. Default value 0.

`rtx_type = 0|1'

`rtx_type = 0|1'

     If 1 (true) use a socket interface to the Ethernet (see parameter

     If 1 (true) use a socket interface to the Ethernet (see parameter

          Note: By default the socket interface is not provided in

          Note: By default the socket interface is not provided in

          Or1ksim. If it is required, this must be requested when

          Or1ksim. If it is required, this must be requested when

          configuring, by use of the `--enable-ethphy' option to

          configuring, by use of the `--enable-ethphy' option to

          `configure'.

          `configure'.

`txfile = "TXFILE"'

`txfile = "TXFILE"'

     When `rtx_type' is 0 (see above), RXFILE specifies the file to use

     When `rtx_type' is 0 (see above), RXFILE specifies the file to use

     as input and TXFILE specifies the fie to use as output.

     as input and TXFILE specifies the fie to use as output.

     The file contains a sequence of packets. Each packet consists of a

     The file contains a sequence of packets. Each packet consists of a

     parameters are `"eth_rx"' and `"eth_tx"' respectively.

     parameters are `"eth_rx"' and `"eth_tx"' respectively.

     The input file must exist and be readable. The output file must be

     The input file must exist and be readable. The output file must be

     writable and will be created if necessary. If either of these

     writable and will be created if necessary. If either of these

     conditions is not met, a warning will be given.

     conditions is not met, a warning will be given.

Or1ksim models a VGA interface to an external monitor.  The VGA

Or1ksim models a VGA interface to an external monitor.  The VGA

controller used in Or1ksim is the component implemented at OpenCores,

controller used in Or1ksim is the component implemented at OpenCores,

and found in the top level CVS directory, `vga_lcd', with no support

and found in the top level CVS directory, `vga_lcd', with no support

for the optional hardware cursors. It is described in the document

for the optional hardware cursors. It is described in the document

`VGA/LCD Core v2.0 Specifications' by Richard Herveille, which can be

`VGA/LCD Core v2.0 Specifications' by Richard Herveille, which can be

The current implementation provides only functionality to dump the

The current implementation provides only functionality to dump the

screen to a file at intervals.

screen to a file at intervals.

VGA controller configuration is described in `section vga'. This

VGA controller configuration is described in `section vga'. This

     If 1 (true, the default), this frame buffer is enabled. If 0, it

     If 1 (true, the default), this frame buffer is enabled. If 0, it

     is disabled.

     is disabled.

`baseaddr = VALUE'

`baseaddr = VALUE'

     Set the base address of the frame buffer's memory mapped registers

     Set the base address of the frame buffer's memory mapped registers

     The frame buffer has an 121-bit address bus, with 4 32-bit

     The frame buffer has an 121-bit address bus, with 4 32-bit

     registers, at addresses 0x000 through 0x00c, and a PAL lookup

     registers, at addresses 0x000 through 0x00c, and a PAL lookup

     table at addresses 0x400 through 0x4ff. Addresses 0x010 through

     table at addresses 0x400 through 0x4ff. Addresses 0x010 through

     0x3fc and addresses 0x500 through 0x7ff are not used.

     0x3fc and addresses 0x500 through 0x7ff are not used.

The implementation only provides for keyboard support, which is

The implementation only provides for keyboard support, which is

modelled as a file of keystrokes. There is no mouse support.

modelled as a file of keystrokes. There is no mouse support.

     Caution: A standard i8042 device has two registers at addresses

     Caution: A standard i8042 device has two registers at addresses

     The port of Linux for the OpenRISC 1000, which runs on Or1ksim

     The port of Linux for the OpenRISC 1000, which runs on Or1ksim

     implements the i8042 device driver, anticipating these registers

     implements the i8042 device driver, anticipating these registers

     reside at their conventional address. It seems unlikel that this

     reside at their conventional address. It seems unlikel that this

     code will work.

     code will work.

The ATA/ATAPI disc controller used in Or1ksim is the OCIDEC (OpenCores

The ATA/ATAPI disc controller used in Or1ksim is the OCIDEC (OpenCores

IDE Controller) component implemented at OpenCores, and found in the

IDE Controller) component implemented at OpenCores, and found in the

top level CVS directory, `ata'. It is described in the document

top level CVS directory, `ata'. It is described in the document

`ATA/ATAPI-5 Core Specification' by Richard Herveille, which can be

`ATA/ATAPI-5 Core Specification' by Richard Herveille, which can be

following parameters may be specified.

following parameters may be specified.

`enabled = 0|1'

`enabled = 0|1'

     If 1 (true, the default), this ATA/ATAPI interface is enabled. If

     If 1 (true, the default), this ATA/ATAPI interface is enabled. If

     0, it is disabled.

     0, it is disabled.

     Set the base address of the ATA/ATAPI interface's memory mapped

     Set the base address of the ATA/ATAPI interface's memory mapped

     registers to VALUE. The default is 0, which is probably not a

     registers to VALUE. The default is 0, which is probably not a

     sensible value.

     sensible value.

     The ATA/ATAPI PS/2 interface has an 5-bit address bus, with 8

     The ATA/ATAPI PS/2 interface has an 5-bit address bus, with 8

`irq = VALUE'

`irq = VALUE'

     Use VALUE as the IRQ number of this ATA/ATAPI interface. Default

     Use VALUE as the IRQ number of this ATA/ATAPI interface. Default

     value 0.

     value 0.

`dma_mode0_td = VALUE'

`dma_mode0_td = VALUE'

`dma_mode0_teoc = VALUE'

`dma_mode0_teoc = VALUE'

     These parameters specify the timings for use with DMA transfers.

     These parameters specify the timings for use with DMA transfers.

     They are specified as the number of clock cycles - 2, rounded up

     They are specified as the number of clock cycles - 2, rounded up

     to the next highest integer, or zero if that would be negative.

     to the next highest integer, or zero if that would be negative.

     See the ATA/ATAPI-5 specification for explanations of each of these

     See the ATA/ATAPI-5 specification for explanations of each of these

     timing parameters. The default values are:

     timing parameters. The default values are:

          dma_mode0_tm   =  4

          dma_mode0_tm   =  4

Within the `section ata', each device is specified separately. The

Within the `section ata', each device is specified separately. The

device subsection is introduced by

device subsection is introduced by

     device VALUE

     device VALUE

`type = VALUE'

`type = VALUE'

     VALUEspecifies the type of device: 0 (the default) for "not

     VALUEspecifies the type of device: 0 (the default) for "not

     connected", 1 for hard disk simulated in a file and 2 for local

     connected", 1 for hard disk simulated in a file and 2 for local

     system hard disk.

     system hard disk.

`pr REG VALUE'

`pr REG VALUE'

     Patch register REG with VALUE.

     Patch register REG with VALUE.

`dm FROMADDR [ TOADDR ]'

`dm FROMADDR [ TOADDR ]'

          Caution: The output from this command is broken (a bug).

          Caution: The output from this command is broken (a bug).

          Or1ksim attempts to print out 16 bytes per row. However,

          Or1ksim attempts to print out 16 bytes per row. However,

          instead of printing out the address at the start of each row,

          instead of printing out the address at the start of each row,

          it prints the address (of the first of the 16 bytes) before

          it prints the address (of the first of the 16 bytes) before

`breaks'

`breaks'

     List all set breakpoints

     List all set breakpoints

`reset'

`reset'

`hist'

`hist'

     If saving the execution history has been configured (*note

     If saving the execution history has been configured (*note

     Simulator Behavior: Simulator Behavior.), display the execution

     Simulator Behavior: Simulator Behavior.), display the execution

     history.

     history.

     When stalled, the processor can execute no instructions. This

     When stalled, the processor can execute no instructions. This

     command is useful when debugging the JTAG interface, used by

     command is useful when debugging the JTAG interface, used by

     debuggers such as GDB.

     debuggers such as GDB.

`unstall'

`unstall'

     debuggers such as GDB.

     debuggers such as GDB.

`stats CATEGORY | clear'

`stats CATEGORY | clear'

     Print the statistics for the given CATEGORY, if available, or

     Print the statistics for the given CATEGORY, if available, or

     clear if `clear' is specified. The categories are:

     clear if `clear' is specified. The categories are:

     Run the memory profiling utility. This follows the same usage as

     Run the memory profiling utility. This follows the same usage as

     the standalone command (*note Memory Profiling Utility: Memory

     the standalone command (*note Memory Profiling Utility: Memory

     Profiling Utility.).

     Profiling Utility.).

`profile [-vhcq] [-g FILE]'

`profile [-vhcq] [-g FILE]'

For all commands, it is possible to redirect the output to a file, by

For all commands, it is possible to redirect the output to a file, by

using the redirection operator, `>'.

using the redirection operator, `>'.

5 Verification API (VAPI)

5 Verification API (VAPI)

*************************

*************************

The Verification API (VAPI) provides a TCP/IP interface to allow

The Verification API (VAPI) provides a TCP/IP interface to allow

with a single piece of data (also a 32 bit integer). On the send side,

with a single piece of data (also a 32 bit integer). On the send side,

it provides for sending a single VAPI ID and data. However there is no

it provides for sending a single VAPI ID and data. However there is no

explicit command-response structure. Some components just accept

explicit command-response structure. Some components just accept

requests (e.g. to set values), some just generate sends (to report

requests (e.g. to set values), some just generate sends (to report

values), and some do both.

values), and some do both.

          The UART skew is set from the least significant 16 bits of

          The UART skew is set from the least significant 16 bits of

          the data

          the data

    `0x04'

    `0x04'

          If the 16th most significant bit of the data is 1, start

          If the 16th most significant bit of the data is 1, start

DMA

DMA

     Although the DMA unit supports a base VAPI ID in its configuration

     Although the DMA unit supports a base VAPI ID in its configuration

     (`section dma'), no VAPI data is sent, nor VAPI requests currently

     (`section dma'), no VAPI data is sent, nor VAPI requests currently

          addresses (`oraddr_t'), unsigned register values (`uorreg_t')

          addresses (`oraddr_t'), unsigned register values (`uorreg_t')

          and signed register (`orreg_t') values.

          and signed register (`orreg_t') values.

     Where new types are defined, they should appear in one of these two

     Where new types are defined, they should appear in one of these two

_Don't begin names with underscore_

_Don't begin names with underscore_

     Names beginning with `_' are intended to be part of the C

     Names beginning with `_' are intended to be part of the C

     infrastructure. They should not be used in the simulator code.

     infrastructure. They should not be used in the simulator code.

_Use of `inline'_

_Use of `inline'_

     Code should not be declared `inline'. Modern compilers can work

     Code should not be declared `inline'. Modern compilers can work

     out for themselves what is best in this respect.

     out for themselves what is best in this respect.

_Initialization_

_Initialization_

     The rationale is that in future static data structures may become

     The rationale is that in future static data structures may become

     dynamic. This has been a particular source of bugs in Or1ksim

     dynamic. This has been a particular source of bugs in Or1ksim

     historically.

     historically.

     `config.sim'.

     `config.sim'.

`config'

`config'

     This is a linked list of data structures holding configuration data

     This is a linked list of data structures holding configuration data

     for all sections which are not held in the main `config' data

     for all sections which are not held in the main `config' data

`runtime'

`runtime'

     The global variable `runtime' of type `struct runtime' holds all

     The global variable `runtime' of type `struct runtime' holds all

     the runtime information about the simulation. To access this

     the runtime information about the simulation. To access this

     variable, `sim-config.h' must be included.

     variable, `sim-config.h' must be included.

6.4 Internal Debugging

6.4 Internal Debugging

======================

======================

The function `debug' is like `printf', but with an extra first

The function `debug' is like `printf', but with an extra first

File: or1ksim.info,  Node: GNU Free Documentation License,  Next: Index,  Prev: Code Internals,  Up: Top

File: or1ksim.info,  Node: GNU Free Documentation License,  Next: Index,  Prev: Code Internals,  Up: Top

7 GNU Free Documentation License

7 GNU Free Documentation License

* Menu:

* Menu:

* --cumulative:                          Profiling Utility.   (line  26)

* --cumulative:                          Profiling Utility.   (line  26)

* --debug-config:                        Standalone Simulator.

* --debug-config:                        Standalone Simulator.

                                                              (line  48)

                                                              (line  48)

* --disable-arith-flag:                  Configuring the Build.

* --disable-arith-flag:                  Configuring the Build.

                                                              (line  93)

                                                              (line  93)

* --disable-debug:                       Configuring the Build.

* --disable-debug:                       Configuring the Build.

                                                              (line 121)

                                                              (line 121)

* --disable-ethphy:                      Configuring the Build.

* --disable-ethphy:                      Configuring the Build.

                                                              (line  70)

                                                              (line  70)

* --disable-profiling:                   Configuring the Build.

* --disable-profiling:                   Configuring the Build.

                                                              (line  25)

                                                              (line  25)

* --disable-range-stats:                 Configuring the Build.

* --disable-range-stats:                 Configuring the Build.

                                                              (line  64)

                                                              (line  64)

* --enable-arith-flag:                   Configuring the Build.

* --enable-arith-flag:                   Configuring the Build.

                                                              (line  92)

                                                              (line  92)

* --enable-debug:                        Configuring the Build.

* --enable-debug:                        Configuring the Build.

                                                              (line 120)

                                                              (line 120)

* --enable-ethphy:                       Configuring the Build.

* --enable-ethphy:                       Configuring the Build.

* 0x03 UART VAPI sub-command (UART verification): Verification API.

* 0x03 UART VAPI sub-command (UART verification): Verification API.

                                                              (line  62)

                                                              (line  62)

* 0x04 UART VAPI sub-command (UART verification): Verification API.

* 0x04 UART VAPI sub-command (UART verification): Verification API.

                                                              (line  66)

                                                              (line  66)

* 16550 (UART configuration):            UART Configuration.  (line  73)

* 16550 (UART configuration):            UART Configuration.  (line  73)

* Argtable2 debugging:                   Configuring the Build.

* Argtable2 debugging:                   Configuring the Build.

                                                              (line 121)

                                                              (line 121)

* ATA/ATAPI configuration:               Disc Interface Configuration.

* ATA/ATAPI configuration:               Disc Interface Configuration.

                                                              (line   6)

                                                              (line   6)

* ATA/ATAPI device configuration:        Disc Interface Configuration.

* ATA/ATAPI device configuration:        Disc Interface Configuration.

* baseaddr (keyboard configuration):     Keyboard Configuration.

* baseaddr (keyboard configuration):     Keyboard Configuration.

                                                              (line  36)

                                                              (line  36)

* baseaddr (memory configuration):       Memory Configuration.

* baseaddr (memory configuration):       Memory Configuration.

                                                              (line  62)

                                                              (line  62)

* baseaddr (memory controller configuration): Memory Controller Configuration.

* baseaddr (memory controller configuration): Memory Controller Configuration.

* baseaddr (UART configuration):         UART Configuration.  (line  22)

* baseaddr (UART configuration):         UART Configuration.  (line  22)

* baseaddr (VGA configuration):          Display Interface Configuration.

* baseaddr (VGA configuration):          Display Interface Configuration.

                                                              (line  26)

                                                              (line  26)

* blocksize (cache configuration):       Cache Configuration. (line  29)

* blocksize (cache configuration):       Cache Configuration. (line  29)

* BPB configuration:                     Branch Prediction Configuration.

* BPB configuration:                     Branch Prediction Configuration.