| Line 62... |
Line 62... |
===============
|
===============
|
|
|
Unpack the software and create a _separate_ directory in which to build
|
Unpack the software and create a _separate_ directory in which to build
|
it:
|
it:
|
|
|
tar jxf or1ksim-2010-05-02.tar.bz2
|
tar jxf or1ksim-2010-05-19.tar.bz2
|
mkdir builddir_or1ksim
|
mkdir builddir_or1ksim
|
cd builddir_or1ksim
|
cd builddir_or1ksim
|
|
|
|
|
File: or1ksim.info, Node: Configuring the Build, Next: Build and Install, Prev: Preparation, Up: Installation
|
File: or1ksim.info, Node: Configuring the Build, Next: Build and Install, Prev: Preparation, Up: Installation
|
| Line 79... |
Line 79... |
|
|
The most significant argument is `--target', which should specify the
|
The most significant argument is `--target', which should specify the
|
OpenRISC 1000 32-bit architecture. If this argument is omitted, it will
|
OpenRISC 1000 32-bit architecture. If this argument is omitted, it will
|
default to OpenRISC 1000 32-bit with a warning
|
default to OpenRISC 1000 32-bit with a warning
|
|
|
../or1ksim-2010-05-02/configure --target=or32-uclinux ...
|
../or1ksim-2010-05-19/configure --target=or32-uclinux ...
|
|
|
There are several other options available, many of which are standard
|
There are several other options available, many of which are standard
|
to GNU `configure' scripts. Use `configure --help' to see all the
|
to GNU `configure' scripts. Use `configure --help' to see all the
|
options. The most useful is `--prefix' to specify a directory for
|
options. The most useful is `--prefix' to specify a directory for
|
installation of the tools.
|
installation of the tools.
|
| Line 241... |
Line 241... |
|
|
1.4 Known Problems and Issues
|
1.4 Known Problems and Issues
|
=============================
|
=============================
|
|
|
The following problems and issues are known about with Or1ksim
|
The following problems and issues are known about with Or1ksim
|
2010-05-02. The OpenRISC tracker may be used to see the current state
|
2010-05-19. The OpenRISC tracker may be used to see the current state
|
of these issues and to raise new problems and feature requests. It may
|
of these issues and to raise new problems and feature requests. It may
|
be found at `http://www.opencores.org/ptracker.cgi/view/or1k/398'.
|
be found at `http://www.opencores.org/ptracker.cgi/view/or1k/398'.
|
|
|
* The Supervision Register Little Endian Enable (LEE) bit is
|
* The Supervision Register Little Endian Enable (LEE) bit is
|
ignored. Or1ksim can be built for either little endian or big
|
ignored. Or1ksim can be built for either little endian or big
|
| Line 1037... |
Line 1037... |
`sr = VALUE'
|
`sr = VALUE'
|
Sets the supervision register Special Purpose Register (SPR 0x11)
|
Sets the supervision register Special Purpose Register (SPR 0x11)
|
to VALUE. Default value is 0x00008001, i.e. start in supervision
|
to VALUE. Default value is 0x00008001, i.e. start in supervision
|
mode (0x00000001) and set the "Fixed One" bit (0x00008000).
|
mode (0x00000001) and set the "Fixed One" bit (0x00008000).
|
|
|
|
Note: This is particularly useful when an image is held in
|
|
Flash at high memory (0xf0000000). The EPH bit can be set,
|
|
so that interrupt vectors are basedf at 0xf0000000, rather
|
|
than 0x0.
|
|
|
`superscalar = 0|1'
|
`superscalar = 0|1'
|
If 1, the processor operates in superscalar mode. Default value is
|
If 1, the processor operates in superscalar mode. Default value is
|
0.
|
0.
|
|
|
In the current simulator, the only functional effect of superscalar
|
In the current simulator, the only functional effect of superscalar
|
| Line 1092... |
Line 1097... |
|
|
3.3.2 Memory Configuration
|
3.3.2 Memory Configuration
|
--------------------------
|
--------------------------
|
|
|
Memory configuration is described in `section memory'. This section
|
Memory configuration is described in `section memory'. This section
|
may appear multiple times, specifying multiple blocks of memory. The
|
may appear multiple times, specifying multiple blocks of memory.
|
following parameters may be specified.
|
|
|
Caution: The user may choose whether or not to enable a memory
|
|
controller. If a memory controller is enabled, then the standard
|
|
OpenRISC C libraries will initialize it to expect 64MB memory
|
|
blocks, and any memory declarations _must_ reflect this. The
|
|
section describing memory controller configuration describes the
|
|
steps necessary for using smaller or larger memory sections (*note
|
|
Memory Controller Configuration: Memory Controller Configuration.).
|
|
|
|
If a memory controller is _not_ enabled, then the standard C
|
|
library code will generate memory access errors. The solution is
|
|
to declare an additional writable memory block, mimicing the memory
|
|
controller's register bank as follows.
|
|
|
|
section memory
|
|
pattern = 0x00
|
|
type = unknown
|
|
name = "MC shadow"
|
|
baseaddr = 0x93000000
|
|
size = 0x00000080
|
|
delayr = 2
|
|
delayw = 4
|
|
end
|
|
|
|
|
|
The following parameters may be specified.
|
|
|
`type=random|pattern|unknown|zero'
|
`type=random|pattern|unknown|zero'
|
Specifies the values to which memory should be initialized. The
|
Specifies the values to which memory should be initialized. The
|
default value is `unknown'.
|
default value is `unknown'.
|
|
|
| Line 1182... |
Line 1212... |
Set the chip enable index of the memory instance. Each memory
|
Set the chip enable index of the memory instance. Each memory
|
instance should have a unique chip enable index, which should be
|
instance should have a unique chip enable index, which should be
|
greater than or equal to zero. This is used by the memory
|
greater than or equal to zero. This is used by the memory
|
controller when identifying different memory instances.
|
controller when identifying different memory instances.
|
|
|
The default value is -1 (invalid).
|
There is no requirement to set `ce' if a memory controller is not
|
|
enabled. The default value is -1 (invalid).
|
|
|
`mc = VALUE'
|
`mc = VALUE'
|
Specifies the memory controller this memory is connected to. It
|
Specifies the memory controller this memory is connected to. It
|
should correspond to the `index' field specified in a `section mc'
|
should correspond to the `index' field specified in a `section mc'
|
for a memory controller (*note Memory Controller Configuration:
|
for a memory controller (*note Memory Controller Configuration:
|
Memory Controller Configuration.).
|
Memory Controller Configuration.).
|
|
|
Default value is 0, which is also the default value of a memory
|
There is no requirement to set `mc' if a memory controller is not
|
controller `index' field. This is suitable therefore for designs
|
enabled. Default value is 0, which is also the default value of a
|
with just one memory controller.
|
memory controller `index' field. This is suitable therefore for
|
|
designs with just one memory controller.
|
|
|
`delayr = VALUE'
|
`delayr = VALUE'
|
The number of cycles required for a read access. Set to -1 if the
|
The number of cycles required for a read access. Set to -1 if the
|
memory does not support reading. Default value 1. The simulator
|
memory does not support reading. Default value 1. The simulator
|
will add this number of cycles to the total instruction cycle
|
will add this number of cycles to the total instruction cycle
|
| Line 1552... |
Line 1584... |
|
|
3.4.1 Memory Controller Configuration
|
3.4.1 Memory Controller Configuration
|
-------------------------------------
|
-------------------------------------
|
|
|
The memory controller used in Or1ksim is the component implemented at
|
The memory controller used in Or1ksim is the component implemented at
|
OpenCores, and found in the top level CVS directory, `mem_ctrl'. It is
|
OpenCores, and found in the top level SVN directory, `mem_ctrl'. It is
|
described in the document `Memory Controller IP Core' by Rudolf
|
described in the document `Memory Controller IP Core' by Rudolf
|
Usselmann, which can be found in the `doc' subdirectory. It is a
|
Usselmann, which can be found in the `doc' subdirectory. It is a
|
memory mapped component, which resides on the main OpenRISC Wishbone
|
memory mapped component, which resides on the main OpenRISC Wishbone
|
data bus.
|
data bus.
|
|
|
The memory controller configuration is described in `section mc'. This
|
The memory controller configuration is described in `section mc'. This
|
section may appear multiple times, specifying multiple memory
|
section may appear multiple times, specifying multiple memory
|
controllers. The following parameters may be specified.
|
controllers.
|
|
|
|
Caution: The standard OpenRISC C libraries will initialize the
|
|
memory controller to expect 64MB memory blocks, and any memory
|
|
declarations _must_ reflect this.
|
|
|
|
If smaller memory blocks are declared with a memory controller,
|
|
then sufficient memory will not be allocated by Or1ksim, but out of
|
|
range memory accesses will not be trapped. For example declaring a
|
|
memory section from 0-4MB with a memory controller enabled would
|
|
mean that accesses between 4MB and 64MB would be permitted, but
|
|
having no allocated memory would likely cause a segmentation fault.
|
|
|
|
If the user is determined to use smaller memories with the memory
|
|
controller, then custom initialization code must be provided, to
|
|
ensure the memory controller traps out-of-memory accesses.
|
|
|
|
The following parameters may be specified.
|
|
|
`enabled = 0|1'
|
`enabled = 0|1'
|
If 1 (true, the default), this memory controller is enabled. If
|
If 1 (true, the default), this memory controller is enabled. If
|
0, it is disabled.
|
0, it is disabled.
|
|
|
| Line 1704... |
Line 1753... |
|
|
3.4.3 DMA Configuration
|
3.4.3 DMA Configuration
|
-----------------------
|
-----------------------
|
|
|
The DMA controller used in Or1ksim is the component implemented at
|
The DMA controller used in Or1ksim is the component implemented at
|
OpenCores, and found in the top level CVS directory, `wb_dma'. It is
|
OpenCores, and found in the top level SVN directory, `wb_dma'. It is
|
described in the document `Wishbone DMA/Bridge IP Core' by Rudolf
|
described in the document `Wishbone DMA/Bridge IP Core' by Rudolf
|
Usselmann, which can be found in the `doc' subdirectory. It is a
|
Usselmann, which can be found in the `doc' subdirectory. It is a
|
memory mapped component, which resides on the main OpenRISC Wishbone
|
memory mapped component, which resides on the main OpenRISC Wishbone
|
data bus. The present implementation is incomplete, intended only to
|
data bus. The present implementation is incomplete, intended only to
|
support the Ethernet interface (*note Ethernet Configuration::),
|
support the Ethernet interface (*note Ethernet Configuration::),
|
| Line 1748... |
Line 1797... |
|
|
3.4.4 Ethernet Configuration
|
3.4.4 Ethernet Configuration
|
----------------------------
|
----------------------------
|
|
|
The Ethernet MAC used in Or1ksim is the component implemented at
|
The Ethernet MAC used in Or1ksim is the component implemented at
|
OpenCores, and found in the top level CVS directory, `ethernet'. It
|
OpenCores, and found in the top level SVN directory, `ethmac'. It also
|
also forms part of the OpenRISC SoC, ORPSoC. It is described in the
|
forms part of the OpenRISC SoC, ORPSoC. It is described in the
|
document `Ethernet IP Core Specification' by Igor Mohor, which can be
|
document `Ethernet IP Core Specification' by Igor Mohor, which can be
|
found in the `doc' subdirectory. It is a memory mapped component,
|
found in the `doc' subdirectory. It is a memory mapped component,
|
which resides on the main OpenRISC Wishbone data bus.
|
which resides on the main OpenRISC Wishbone data bus.
|
|
|
Ethernet configuration is described in `section ethernet'. This
|
Ethernet configuration is described in `section ethernet'. This
|
| Line 1842... |
Line 1891... |
|
|
3.4.5 GPIO Configuration
|
3.4.5 GPIO Configuration
|
------------------------
|
------------------------
|
|
|
The GPIO used in Or1ksim is the component implemented at OpenCores, and
|
The GPIO used in Or1ksim is the component implemented at OpenCores, and
|
found in the top level CVS directory, `gpio'. It is described in the
|
found in the top level SVN directory, `gpio'. It is described in the
|
document `GPIO IP Core Specification' by Damjan Lampret and Goran
|
document `GPIO IP Core Specification' by Damjan Lampret and Goran
|
Djakovic, which can be found in the `doc' subdirectory. It is a memory
|
Djakovic, which can be found in the `doc' subdirectory. It is a memory
|
mapped component, which resides on the main OpenRISC Wishbone data bus.
|
mapped component, which resides on the main OpenRISC Wishbone data bus.
|
|
|
GPIO configuration is described in `section gpio'. This section may
|
GPIO configuration is described in `section gpio'. This section may
|
| Line 1883... |
Line 1932... |
3.4.6 Display Interface Configuration
|
3.4.6 Display Interface Configuration
|
-------------------------------------
|
-------------------------------------
|
|
|
Or1ksim models a VGA interface to an external monitor. The VGA
|
Or1ksim models a VGA interface to an external monitor. The VGA
|
controller used in Or1ksim is the component implemented at OpenCores,
|
controller used in Or1ksim is the component implemented at OpenCores,
|
and found in the top level CVS directory, `vga_lcd', with no support
|
and found in the top level SVN directory, `vga_lcd', with no support
|
for the optional hardware cursors. It is described in the document
|
for the optional hardware cursors. It is described in the document
|
`VGA/LCD Core v2.0 Specifications' by Richard Herveille, which can be
|
`VGA/LCD Core v2.0 Specifications' by Richard Herveille, which can be
|
found in the `doc' subdirectory. It is a memory mapped component,
|
found in the `doc' subdirectory. It is a memory mapped component,
|
which resides on the main OpenRISC Wishbone data bus.
|
which resides on the main OpenRISC Wishbone data bus.
|
|
|
| Line 1981... |
Line 2030... |
|
|
3.4.8 Keyboard Configuration (PS2)
|
3.4.8 Keyboard Configuration (PS2)
|
----------------------------------
|
----------------------------------
|
|
|
The PS2 interface provided by Or1ksim is not documented. It may be
|
The PS2 interface provided by Or1ksim is not documented. It may be
|
based on the PS2 project at OpenCores, and found in the top level CVS
|
based on the PS2 project at OpenCores, and found in the top level SVN
|
directory, `ps2'. However this project lacks any documentation beyond
|
directory, `ps2'. However this project lacks any documentation beyond
|
its project webpage. Since most PS2 interfaces follow the Intel i8042
|
its project webpage. Since most PS2 interfaces follow the Intel i8042
|
standard, this is presumably what is expected with this device.
|
standard, this is presumably what is expected with this device.
|
|
|
The implementation only provides for keyboard support, which is
|
The implementation only provides for keyboard support, which is
|
| Line 2038... |
Line 2087... |
3.4.9 Disc Interface Configuration
|
3.4.9 Disc Interface Configuration
|
----------------------------------
|
----------------------------------
|
|
|
The ATA/ATAPI disc controller used in Or1ksim is the OCIDEC (OpenCores
|
The ATA/ATAPI disc controller used in Or1ksim is the OCIDEC (OpenCores
|
IDE Controller) component implemented at OpenCores, and found in the
|
IDE Controller) component implemented at OpenCores, and found in the
|
top level CVS directory, `ata'. It is described in the document
|
top level SVN directory, `ata'. It is described in the document
|
`ATA/ATAPI-5 Core Specification' by Richard Herveille, which can be
|
`ATA/ATAPI-5 Core Specification' by Richard Herveille, which can be
|
found in the `doc' subdirectory. It is a memory mapped component,
|
found in the `doc' subdirectory. It is a memory mapped component,
|
which resides on the main OpenRISC Wishbone data bus.
|
which resides on the main OpenRISC Wishbone data bus.
|
|
|
ATA/ATAPI configuration is described in `section ata'. This section
|
ATA/ATAPI configuration is described in `section ata'. This section
|
| Line 3343... |
Line 3392... |
(line 22)
|
(line 22)
|
* baseaddr (GPIO configuration): GPIO Configuration. (line 21)
|
* baseaddr (GPIO configuration): GPIO Configuration. (line 21)
|
* baseaddr (keyboard configuration): Keyboard Configuration.
|
* baseaddr (keyboard configuration): Keyboard Configuration.
|
(line 36)
|
(line 36)
|
* baseaddr (memory configuration): Memory Configuration.
|
* baseaddr (memory configuration): Memory Configuration.
|
(line 62)
|
(line 87)
|
* baseaddr (memory controller configuration): Memory Controller Configuration.
|
* baseaddr (memory controller configuration): Memory Controller Configuration.
|
(line 29)
|
(line 46)
|
* baseaddr (UART configuration): UART Configuration. (line 22)
|
* baseaddr (UART configuration): UART Configuration. (line 22)
|
* baseaddr (VGA configuration): Display Interface Configuration.
|
* baseaddr (VGA configuration): Display Interface Configuration.
|
(line 26)
|
(line 26)
|
* blocksize (cache configuration): Cache Configuration. (line 29)
|
* blocksize (cache configuration): Cache Configuration. (line 29)
|
* BPB configuration: Branch Prediction Configuration.
|
* BPB configuration: Branch Prediction Configuration.
|
| Line 3369... |
Line 3418... |
* byte_enabled (generic peripheral configuration): Generic Peripheral Configuration.
|
* byte_enabled (generic peripheral configuration): Generic Peripheral Configuration.
|
(line 48)
|
(line 48)
|
* cache configuration: Cache Configuration. (line 6)
|
* cache configuration: Cache Configuration. (line 6)
|
* calling_convention (CUC configuration): CUC Configuration. (line 34)
|
* calling_convention (CUC configuration): CUC Configuration. (line 34)
|
* ce (memory configuration): Memory Configuration.
|
* ce (memory configuration): Memory Configuration.
|
(line 92)
|
(line 117)
|
* cfgr (CPU configuration): CPU Configuration. (line 47)
|
* cfgr (CPU configuration): CPU Configuration. (line 47)
|
* channel (UART configuration): UART Configuration. (line 29)
|
* channel (UART configuration): UART Configuration. (line 29)
|
* clear breakpoint (Interactive CLI): Interactive Command Line.
|
* clear breakpoint (Interactive CLI): Interactive Command Line.
|
(line 57)
|
(line 57)
|
* clkcycle (simulator configuration): Simulator Behavior. (line 103)
|
* clkcycle (simulator configuration): Simulator Behavior. (line 103)
|
| Line 3478... |
Line 3527... |
(line 6)
|
(line 6)
|
* Debug Unit verification (VAPI): Verification API. (line 34)
|
* Debug Unit verification (VAPI): Verification API. (line 34)
|
* debugging enabled (Argtable2): Configuring the Build.
|
* debugging enabled (Argtable2): Configuring the Build.
|
(line 121)
|
(line 121)
|
* delayr (memory configuration): Memory Configuration.
|
* delayr (memory configuration): Memory Configuration.
|
(line 110)
|
(line 137)
|
* delayw (memory configuration): Memory Configuration.
|
* delayw (memory configuration): Memory Configuration.
|
(line 116)
|
(line 143)
|
* dependstats (CPU configuration): CPU Configuration. (line 84)
|
* dependstats (CPU configuration): CPU Configuration. (line 89)
|
* dev_id (ATA/ATAPI configuration): Disc Interface Configuration.
|
* dev_id (ATA/ATAPI configuration): Disc Interface Configuration.
|
(line 36)
|
(line 36)
|
* disassemble (Interactive CLI): Interactive Command Line.
|
* disassemble (Interactive CLI): Interactive Command Line.
|
(line 41)
|
(line 41)
|
* disc interface configuration: Disc Interface Configuration.
|
* disc interface configuration: Disc Interface Configuration.
|
| Line 3545... |
Line 3594... |
* enabled (interrupt controller): Interrupt Configuration.
|
* enabled (interrupt controller): Interrupt Configuration.
|
(line 12)
|
(line 12)
|
* enabled (keyboard configuration): Keyboard Configuration.
|
* enabled (keyboard configuration): Keyboard Configuration.
|
(line 32)
|
(line 32)
|
* enabled (memory controller configuration): Memory Controller Configuration.
|
* enabled (memory controller configuration): Memory Controller Configuration.
|
(line 18)
|
(line 35)
|
* enabled (MMU configuration): Memory Management Configuration.
|
* enabled (MMU configuration): Memory Management Configuration.
|
(line 12)
|
(line 12)
|
* enabled (power management configuration): Power Management Configuration.
|
* enabled (power management configuration): Power Management Configuration.
|
(line 35)
|
(line 35)
|
* enabled (UART configuration): UART Configuration. (line 18)
|
* enabled (UART configuration): UART Configuration. (line 18)
|
| Line 3615... |
Line 3664... |
* GPIO_VAPI_CTRL (GPIO verification): Verification API. (line 119)
|
* GPIO_VAPI_CTRL (GPIO verification): Verification API. (line 119)
|
* GPIO_VAPI_DATA (GPIO verification): Verification API. (line 97)
|
* GPIO_VAPI_DATA (GPIO verification): Verification API. (line 97)
|
* GPIO_VAPI_INTE (GPIO verification): Verification API. (line 110)
|
* GPIO_VAPI_INTE (GPIO verification): Verification API. (line 110)
|
* GPIO_VAPI_PTRIG (GPIO verification): Verification API. (line 113)
|
* GPIO_VAPI_PTRIG (GPIO verification): Verification API. (line 113)
|
* GPIO_VAPI_RGPIO (GPIO verification): Verification API. (line 107)
|
* GPIO_VAPI_RGPIO (GPIO verification): Verification API. (line 107)
|
* hazards (CPU configuration): CPU Configuration. (line 69)
|
* hazards (CPU configuration): CPU Configuration. (line 74)
|
* heads (ATA/ATAPI device configuration): Disc Interface Configuration.
|
* heads (ATA/ATAPI device configuration): Disc Interface Configuration.
|
(line 121)
|
(line 121)
|
* help (Interactive CLI): Interactive Command Line.
|
* help (Interactive CLI): Interactive Command Line.
|
(line 170)
|
(line 170)
|
* hexadecimal memory dump (Interactive CLI): Interactive Command Line.
|
* hexadecimal memory dump (Interactive CLI): Interactive Command Line.
|
| Line 3640... |
Line 3689... |
* hw_enabled (generic peripheral configuration): Generic Peripheral Configuration.
|
* hw_enabled (generic peripheral configuration): Generic Peripheral Configuration.
|
(line 49)
|
(line 49)
|
* IMMU configuration: Memory Management Configuration.
|
* IMMU configuration: Memory Management Configuration.
|
(line 6)
|
(line 6)
|
* index (memory controller configuration): Memory Controller Configuration.
|
* index (memory controller configuration): Memory Controller Configuration.
|
(line 51)
|
(line 68)
|
* info (Interactive CLI): Interactive Command Line.
|
* info (Interactive CLI): Interactive Command Line.
|
(line 119)
|
(line 119)
|
* installing Or1ksim: Installation. (line 6)
|
* installing Or1ksim: Installation. (line 6)
|
* instruction cache configuration: Cache Configuration. (line 6)
|
* instruction cache configuration: Cache Configuration. (line 6)
|
* instruction MMU configuration: Memory Management Configuration.
|
* instruction MMU configuration: Memory Management Configuration.
|
| Line 3675... |
Line 3724... |
* load_hitdelay (data cache configuration): Cache Configuration.
|
* load_hitdelay (data cache configuration): Cache Configuration.
|
(line 46)
|
(line 46)
|
* load_missdelay (data cache configuration): Cache Configuration.
|
* load_missdelay (data cache configuration): Cache Configuration.
|
(line 50)
|
(line 50)
|
* log (memory configuration): Memory Configuration.
|
* log (memory configuration): Memory Configuration.
|
(line 122)
|
(line 149)
|
* log_enabled (verification API configuration): Verification API Configuration.
|
* log_enabled (verification API configuration): Verification API Configuration.
|
(line 28)
|
(line 28)
|
* long: Simulator Library. (line 87)
|
* long: Simulator Library. (line 87)
|
* mc (memory configuration): Memory Configuration.
|
* mc (memory configuration): Memory Configuration.
|
(line 100)
|
(line 126)
|
* memory configuration: Memory Configuration.
|
* memory configuration: Memory Configuration.
|
(line 6)
|
(line 6)
|
* memory controller configuration: Memory Controller Configuration.
|
* memory controller configuration: Memory Controller Configuration.
|
(line 6)
|
(line 6)
|
* memory copying (Interactive CLI): Interactive Command Line.
|
* memory copying (Interactive CLI): Interactive Command Line.
|
| Line 3727... |
Line 3776... |
* mwdma (ATA/ATAPI device configuration): Disc Interface Configuration.
|
* mwdma (ATA/ATAPI device configuration): Disc Interface Configuration.
|
(line 128)
|
(line 128)
|
* name (generic peripheral configuration): Generic Peripheral Configuration.
|
* name (generic peripheral configuration): Generic Peripheral Configuration.
|
(line 42)
|
(line 42)
|
* name (memory configuration): Memory Configuration.
|
* name (memory configuration): Memory Configuration.
|
(line 83)
|
(line 108)
|
* no_multicycle (CUC configuration): CUC Configuration. (line 42)
|
* no_multicycle (CUC configuration): CUC Configuration. (line 42)
|
* nsets (cache configuration): Cache Configuration. (line 15)
|
* nsets (cache configuration): Cache Configuration. (line 15)
|
* nsets (MMU configuration): Memory Management Configuration.
|
* nsets (MMU configuration): Memory Management Configuration.
|
(line 16)
|
(line 16)
|
* nways (cache configuration): Cache Configuration. (line 22)
|
* nways (cache configuration): Cache Configuration. (line 22)
|
| Line 3758... |
Line 3807... |
* patching registers (Interactive CLI): Interactive Command Line.
|
* patching registers (Interactive CLI): Interactive Command Line.
|
(line 28)
|
(line 28)
|
* patching the program counter (Interactive CLI): Interactive Command Line.
|
* patching the program counter (Interactive CLI): Interactive Command Line.
|
(line 51)
|
(line 51)
|
* pattern (memory configuration): Memory Configuration.
|
* pattern (memory configuration): Memory Configuration.
|
(line 50)
|
(line 75)
|
* pc (Interactive CLI): Interactive Command Line.
|
* pc (Interactive CLI): Interactive Command Line.
|
(line 51)
|
(line 51)
|
* PIC configuration: Interrupt Configuration.
|
* PIC configuration: Interrupt Configuration.
|
(line 6)
|
(line 6)
|
* pio (ATA/ATAPI device configuration): Disc Interface Configuration.
|
* pio (ATA/ATAPI device configuration): Disc Interface Configuration.
|
| Line 3788... |
Line 3837... |
* PMR - SUME: Power Management Configuration.
|
* PMR - SUME: Power Management Configuration.
|
(line 24)
|
(line 24)
|
* PMU configuration: Power Management Configuration.
|
* PMU configuration: Power Management Configuration.
|
(line 6)
|
(line 6)
|
* poc (memory controller configuration): Memory Controller Configuration.
|
* poc (memory controller configuration): Memory Controller Configuration.
|
(line 38)
|
(line 55)
|
* port range for TCP/IP: Verification API Configuration.
|
* port range for TCP/IP: Verification API Configuration.
|
(line 23)
|
(line 23)
|
* power management configuration: Power Management Configuration.
|
* power management configuration: Power Management Configuration.
|
(line 6)
|
(line 6)
|
* power management register, DGCE: Power Management Configuration.
|
* power management register, DGCE: Power Management Configuration.
|
| Line 3832... |
Line 3881... |
* quitting (Interactive CLI): Interactive Command Line.
|
* quitting (Interactive CLI): Interactive Command Line.
|
(line 11)
|
(line 11)
|
* r (Interactive CLI): Interactive Command Line.
|
* r (Interactive CLI): Interactive Command Line.
|
(line 14)
|
(line 14)
|
* random_seed (memory configuration): Memory Configuration.
|
* random_seed (memory configuration): Memory Configuration.
|
(line 40)
|
(line 65)
|
* refresh_rate (frame buffer configuration): Frame Buffer Configuration.
|
* refresh_rate (frame buffer configuration): Frame Buffer Configuration.
|
(line 30)
|
(line 30)
|
* refresh_rate (VGA configuration): Display Interface Configuration.
|
* refresh_rate (VGA configuration): Display Interface Configuration.
|
(line 41)
|
(line 41)
|
* reg_sim_reset: Concepts. (line 13)
|
* reg_sim_reset: Concepts. (line 13)
|
| Line 3884... |
Line 3933... |
(line 68)
|
(line 68)
|
* sbp_bf_fwd (branch prediction configuration): Branch Prediction Configuration.
|
* sbp_bf_fwd (branch prediction configuration): Branch Prediction Configuration.
|
(line 23)
|
(line 23)
|
* sbp_bnf_fwd (branch prediction configuration): Branch Prediction Configuration.
|
* sbp_bnf_fwd (branch prediction configuration): Branch Prediction Configuration.
|
(line 28)
|
(line 28)
|
* sbuf_len (CPU configuration): CPU Configuration. (line 96)
|
* sbuf_len (CPU configuration): CPU Configuration. (line 101)
|
* SDF (power management register): Power Management Configuration.
|
* SDF (power management register): Power Management Configuration.
|
(line 12)
|
(line 12)
|
* section ata: Disc Interface Configuration.
|
* section ata: Disc Interface Configuration.
|
(line 6)
|
(line 6)
|
* section bpb: Branch Prediction Configuration.
|
* section bpb: Branch Prediction Configuration.
|
| Line 3953... |
Line 4002... |
* size (ATA/ATAPI device configuration): Disc Interface Configuration.
|
* size (ATA/ATAPI device configuration): Disc Interface Configuration.
|
(line 109)
|
(line 109)
|
* size (generic peripheral configuration): Generic Peripheral Configuration.
|
* size (generic peripheral configuration): Generic Peripheral Configuration.
|
(line 30)
|
(line 30)
|
* size (memory configuration): Memory Configuration.
|
* size (memory configuration): Memory Configuration.
|
(line 67)
|
(line 92)
|
* sleep mode (power management register): Power Management Configuration.
|
* sleep mode (power management register): Power Management Configuration.
|
(line 16)
|
(line 16)
|
* slow down factor (power management register): Power Management Configuration.
|
* slow down factor (power management register): Power Management Configuration.
|
(line 12)
|
(line 12)
|
* SME (power management register): Power Management Configuration.
|
* SME (power management register): Power Management Configuration.
|
| Line 3981... |
Line 4030... |
(line 54)
|
(line 54)
|
* store_missdelay (data cache configuration): Cache Configuration.
|
* store_missdelay (data cache configuration): Cache Configuration.
|
(line 58)
|
(line 58)
|
* SUME (power management register): Power Management Configuration.
|
* SUME (power management register): Power Management Configuration.
|
(line 24)
|
(line 24)
|
* superscalar (CPU configuration): CPU Configuration. (line 58)
|
* superscalar (CPU configuration): CPU Configuration. (line 63)
|
* suspend mode (power management register): Power Management Configuration.
|
* suspend mode (power management register): Power Management Configuration.
|
(line 24)
|
(line 24)
|
* t (Interactive CLI): Interactive Command Line.
|
* t (Interactive CLI): Interactive Command Line.
|
(line 19)
|
(line 19)
|
* TCP/IP port range: Verification API Configuration.
|
* TCP/IP port range: Verification API Configuration.
|
| Line 4014... |
Line 4063... |
* txfile (VGA configuration): Display Interface Configuration.
|
* txfile (VGA configuration): Display Interface Configuration.
|
(line 47)
|
(line 47)
|
* type (ATA/ATAPI device configuration): Disc Interface Configuration.
|
* type (ATA/ATAPI device configuration): Disc Interface Configuration.
|
(line 99)
|
(line 99)
|
* type (memory configuration): Memory Configuration.
|
* type (memory configuration): Memory Configuration.
|
(line 11)
|
(line 36)
|
* type=pattern (memory configuration): Memory Configuration.
|
* type=pattern (memory configuration): Memory Configuration.
|
(line 21)
|
(line 46)
|
* type=random (memory configuration): Memory Configuration.
|
* type=random (memory configuration): Memory Configuration.
|
(line 15)
|
(line 40)
|
* type=unknown (memory configuration): Memory Configuration.
|
* type=unknown (memory configuration): Memory Configuration.
|
(line 25)
|
(line 50)
|
* type=zero (memory configuration): Memory Configuration.
|
* type=zero (memory configuration): Memory Configuration.
|
(line 29)
|
(line 54)
|
* UART configuration: UART Configuration. (line 6)
|
* UART configuration: UART Configuration. (line 6)
|
* UART I/O from/to a physical serial port: UART Configuration.
|
* UART I/O from/to a physical serial port: UART Configuration.
|
(line 62)
|
(line 62)
|
* UART I/O from/to an xterm: UART Configuration. (line 38)
|
* UART I/O from/to an xterm: UART Configuration. (line 38)
|
* UART I/O from/to files: UART Configuration. (line 33)
|
* UART I/O from/to files: UART Configuration. (line 33)
|
| Line 4092... |
Line 4141... |
Node: Simulator Behavior26164
|
Node: Simulator Behavior26164
|
Node: Verification API Configuration30208
|
Node: Verification API Configuration30208
|
Node: CUC Configuration32148
|
Node: CUC Configuration32148
|
Node: Core OpenRISC Configuration34065
|
Node: Core OpenRISC Configuration34065
|
Node: CPU Configuration34567
|
Node: CPU Configuration34567
|
Node: Memory Configuration38372
|
Node: Memory Configuration38602
|
Node: Memory Management Configuration43685
|
Node: Memory Management Configuration45060
|
Node: Cache Configuration46062
|
Node: Cache Configuration47437
|
Node: Interrupt Configuration48448
|
Node: Interrupt Configuration49823
|
Node: Power Management Configuration49184
|
Node: Power Management Configuration50559
|
Node: Branch Prediction Configuration50461
|
Node: Branch Prediction Configuration51836
|
Node: Debug Interface Configuration51821
|
Node: Debug Interface Configuration53196
|
Node: Peripheral Configuration56041
|
Node: Peripheral Configuration57416
|
Node: Memory Controller Configuration56667
|
Node: Memory Controller Configuration58042
|
Node: UART Configuration59272
|
Node: UART Configuration61456
|
Node: DMA Configuration62791
|
Node: DMA Configuration64975
|
Node: Ethernet Configuration64658
|
Node: Ethernet Configuration66842
|
Node: GPIO Configuration68636
|
Node: GPIO Configuration70818
|
Node: Display Interface Configuration70269
|
Node: Display Interface Configuration72451
|
Node: Frame Buffer Configuration72578
|
Node: Frame Buffer Configuration74760
|
Node: Keyboard Configuration74442
|
Node: Keyboard Configuration76624
|
Node: Disc Interface Configuration76680
|
Node: Disc Interface Configuration78862
|
Node: Generic Peripheral Configuration81623
|
Node: Generic Peripheral Configuration83805
|
Node: Interactive Command Line83918
|
Node: Interactive Command Line86100
|
Node: Verification API90892
|
Node: Verification API93074
|
Node: Code Internals95322
|
Node: Code Internals97504
|
Node: Coding Conventions95882
|
Node: Coding Conventions98064
|
Node: Global Data Structures100309
|
Node: Global Data Structures102491
|
Node: Concepts102966
|
Node: Concepts105148
|
Ref: Output Redirection103111
|
Ref: Output Redirection105293
|
Node: Internal Debugging103650
|
Node: Internal Debugging105832
|
Node: GNU Free Documentation License104147
|
Node: GNU Free Documentation License106329
|
Node: Index126554
|
Node: Index128736
|
|
|
End Tag Table
|
End Tag Table
|
