| Line 1251... |
Line 1251... |
@cindex @code{sr} (CPU configuration)
|
@cindex @code{sr} (CPU configuration)
|
Sets the supervision register Special Purpose Register (SPR 0x11) to
|
Sets the supervision register Special Purpose Register (SPR 0x11) to
|
@var{value}. Default value is 0x00008001, i.e. start in supervision
|
@var{value}. Default value is 0x00008001, i.e. start in supervision
|
mode (0x00000001) and set the ``Fixed One'' bit (0x00008000).
|
mode (0x00000001) and set the ``Fixed One'' bit (0x00008000).
|
|
|
|
@quotation Note
|
|
This is particularly useful when an image is held in Flash at high
|
|
memory (0xf0000000). The EPH bit can be set, so that interrupt
|
|
vectors are basedf at 0xf0000000, rather than 0x0.
|
|
@end quotation
|
|
|
@item superscalar = 0|1
|
@item superscalar = 0|1
|
@cindex @code{superscalar} (CPU configuration)
|
@cindex @code{superscalar} (CPU configuration)
|
If 1, the processor operates in superscalar mode. Default value is
|
If 1, the processor operates in superscalar mode. Default value is
|
0.
|
0.
|
|
|
| Line 1316... |
Line 1322... |
@cindex configuring memory
|
@cindex configuring memory
|
@cindex memory configuration
|
@cindex memory configuration
|
@cindex @code{section memory}
|
@cindex @code{section memory}
|
Memory configuration is described in @code{section memory}. This
|
Memory configuration is described in @code{section memory}. This
|
section may appear multiple times, specifying multiple blocks of
|
section may appear multiple times, specifying multiple blocks of
|
memory. The following parameters may be specified.
|
memory.
|
|
|
|
@quotation Caution
|
|
The user may choose whether or not to enable a memory controller. If a
|
|
memory controller is enabled, then the standard OpenRISC C libraries
|
|
will initialize it to expect 64MB memory blocks, and any memory
|
|
declarations @emph{must} reflect this. The section describing memory
|
|
controller configuration describes the steps necessary for using
|
|
smaller or larger memory sections (@pxref{Memory Controller
|
|
Configuration, , Memory Controller Configuration}).
|
|
|
|
If a memory controller is @emph{not} enabled, then the standard C
|
|
library code will generate memory access errors. The solution is to
|
|
declare an additional writable memory block, mimicing the memory
|
|
controller's register bank as follows.
|
|
|
|
@example
|
|
section memory
|
|
pattern = 0x00
|
|
type = unknown
|
|
name = "MC shadow"
|
|
baseaddr = 0x93000000
|
|
size = 0x00000080
|
|
delayr = 2
|
|
delayw = 4
|
|
end
|
|
@end example
|
|
|
|
@end quotation
|
|
|
|
|
|
The following parameters may be specified.
|
|
|
@table @code
|
@table @code
|
|
|
@item type=random|pattern|unknown|zero
|
@item type=random|pattern|unknown|zero
|
@cindex @code{type} (memory configuration)
|
@cindex @code{type} (memory configuration)
|
| Line 1427... |
Line 1464... |
Set the chip enable index of the memory instance. Each memory instance
|
Set the chip enable index of the memory instance. Each memory instance
|
should have a unique chip enable index, which should be greater
|
should have a unique chip enable index, which should be greater
|
than or equal to zero. This is used by the memory controller when
|
than or equal to zero. This is used by the memory controller when
|
identifying different memory instances.
|
identifying different memory instances.
|
|
|
The default value is -1 (invalid).
|
There is no requirement to set @code{ce} if a memory controller is
|
|
not enabled. The default value is -1 (invalid).
|
|
|
@item mc = @var{value}
|
@item mc = @var{value}
|
@cindex @code{mc} (memory configuration)
|
@cindex @code{mc} (memory configuration)
|
Specifies the memory controller this memory is connected to. It should
|
Specifies the memory controller this memory is connected to. It should
|
correspond to the @code{index} field specified in a @code{@w{section
|
correspond to the @code{index} field specified in a @code{@w{section
|
mc}} for a memory controller (@pxref{Memory Controller Configuration,
|
mc}} for a memory controller (@pxref{Memory Controller Configuration,
|
, Memory Controller Configuration}).
|
, Memory Controller Configuration}).
|
|
|
Default value is 0, which is also the default value of a memory
|
There is no requirement to set @code{mc} if a memory controller is
|
|
not enabled. Default value is 0, which is also the default value of a memory
|
controller @code{index} field. This is suitable therefore for designs
|
controller @code{index} field. This is suitable therefore for designs
|
with just one memory controller.
|
with just one memory controller.
|
|
|
@item delayr = @var{value}
|
@item delayr = @var{value}
|
@cindex @code{delayr} (memory configuration)
|
@cindex @code{delayr} (memory configuration)
|
| Line 1894... |
Line 1933... |
@subsection Memory Controller Configuration
|
@subsection Memory Controller Configuration
|
@cindex configuring the memory controller
|
@cindex configuring the memory controller
|
@cindex memory controller configuration
|
@cindex memory controller configuration
|
@cindex @code{section mc}
|
@cindex @code{section mc}
|
The memory controller used in @value{OR1KSIM} is the component
|
The memory controller used in @value{OR1KSIM} is the component
|
implemented at OpenCores, and found in the top level CVS directory,
|
implemented at OpenCores, and found in the top level SVN directory,
|
@file{mem_ctrl}. It is described in the document @cite{Memory
|
@file{mem_ctrl}. It is described in the document @cite{Memory
|
Controller IP Core} by Rudolf Usselmann, which can be found in the
|
Controller IP Core} by Rudolf Usselmann, which can be found in the
|
@file{doc} subdirectory. It is a memory mapped component, which
|
@file{doc} subdirectory. It is a memory mapped component, which
|
resides on the main OpenRISC Wishbone data bus.
|
resides on the main OpenRISC Wishbone data bus.
|
|
|
The memory controller configuration is described in @code{@w{section
|
The memory controller configuration is described in @code{@w{section
|
mc}}. This section may appear multiple times, specifying multiple
|
mc}}. This section may appear multiple times, specifying multiple
|
memory controllers. The following parameters may be specified.
|
memory controllers.
|
|
|
|
@quotation Caution
|
|
The standard OpenRISC C libraries will initialize the memory
|
|
controller to expect 64MB memory blocks, and any memory declarations
|
|
@emph{must} reflect this.
|
|
|
|
If smaller memory blocks are declared with a memory controller, then
|
|
sufficient memory will not be allocated by @value{OR1KSIM}, but out of
|
|
range memory accesses will not be trapped. For example declaring a
|
|
memory section from 0-4MB with a memory controller enabled would mean
|
|
that accesses between 4MB and 64MB would be permitted, but having no
|
|
allocated memory would likely cause a segmentation fault.
|
|
|
|
If the user is determined to use smaller memories with the memory
|
|
controller, then custom initialization code must be provided, to
|
|
ensure the memory controller traps out-of-memory accesses.
|
|
@end quotation
|
|
|
|
The following parameters may be specified.
|
|
|
@table @code
|
@table @code
|
|
|
@item enabled = 0|1
|
@item enabled = 0|1
|
@cindex @code{enabled} (memory controller configuration)
|
@cindex @code{enabled} (memory controller configuration)
|
| Line 2073... |
Line 2131... |
@subsection DMA Configuration
|
@subsection DMA Configuration
|
@cindex configuring DMA
|
@cindex configuring DMA
|
@cindex DMA configuration
|
@cindex DMA configuration
|
@cindex @code{section dma}
|
@cindex @code{section dma}
|
The DMA controller used in @value{OR1KSIM} is the component
|
The DMA controller used in @value{OR1KSIM} is the component
|
implemented at OpenCores, and found in the top level CVS directory,
|
implemented at OpenCores, and found in the top level SVN directory,
|
@file{wb_dma}. It is described in the document @cite{Wishbone
|
@file{wb_dma}. It is described in the document @cite{Wishbone
|
DMA/Bridge IP Core} by Rudolf Usselmann, which can be found in the
|
DMA/Bridge IP Core} by Rudolf Usselmann, which can be found in the
|
@file{doc} subdirectory. It is a memory mapped component, which
|
@file{doc} subdirectory. It is a memory mapped component, which
|
resides on the main OpenRISC Wishbone data bus. The present
|
resides on the main OpenRISC Wishbone data bus. The present
|
implementation is incomplete, intended only to support the Ethernet
|
implementation is incomplete, intended only to support the Ethernet
|
| Line 2123... |
Line 2181... |
@subsection Ethernet Configuration
|
@subsection Ethernet Configuration
|
@cindex configuring the Ethernet interface
|
@cindex configuring the Ethernet interface
|
@cindex Ethernet configuration
|
@cindex Ethernet configuration
|
@cindex @code{section ethernet}
|
@cindex @code{section ethernet}
|
The Ethernet MAC used in @value{OR1KSIM} is the component implemented
|
The Ethernet MAC used in @value{OR1KSIM} is the component implemented
|
at OpenCores, and found in the top level CVS directory,
|
at OpenCores, and found in the top level SVN directory, @file{ethmac}.
|
@file{ethernet}. It also forms part of the OpenRISC SoC, ORPSoC. It is
|
It also forms part of the OpenRISC SoC, ORPSoC. It is described in
|
described in the document @cite{Ethernet IP Core Specification} by
|
the document @cite{Ethernet IP Core Specification} by Igor Mohor,
|
Igor Mohor, which can be found in the @file{doc} subdirectory. It is a
|
which can be found in the @file{doc} subdirectory. It is a memory
|
memory mapped component, which resides on the main OpenRISC Wishbone
|
mapped component, which resides on the main OpenRISC Wishbone data
|
data bus.
|
bus.
|
|
|
Ethernet configuration is described in @code{section ethernet}. This
|
Ethernet configuration is described in @code{section ethernet}. This
|
section may appear multiple times, specifying multiple Ethernet
|
section may appear multiple times, specifying multiple Ethernet
|
interfaces. The following parameters may be specified.
|
interfaces. The following parameters may be specified.
|
|
|
| Line 2240... |
Line 2298... |
@subsection GPIO Configuration
|
@subsection GPIO Configuration
|
@cindex configuring the GPIO
|
@cindex configuring the GPIO
|
@cindex GPIO configuration
|
@cindex GPIO configuration
|
@cindex @code{section cpio}
|
@cindex @code{section cpio}
|
The GPIO used in @value{OR1KSIM} is the component implemented at
|
The GPIO used in @value{OR1KSIM} is the component implemented at
|
OpenCores, and found in the top level CVS directory, @file{gpio}. It
|
OpenCores, and found in the top level SVN directory, @file{gpio}. It
|
is described in the document @cite{GPIO IP Core Specification} by
|
is described in the document @cite{GPIO IP Core Specification} by
|
Damjan Lampret and Goran Djakovic, which can be found in the
|
Damjan Lampret and Goran Djakovic, which can be found in the
|
@file{doc} subdirectory. It is a memory mapped component, which
|
@file{doc} subdirectory. It is a memory mapped component, which
|
resides on the main OpenRISC Wishbone data bus.
|
resides on the main OpenRISC Wishbone data bus.
|
|
|
| Line 2290... |
Line 2348... |
@cindex display interface configuration
|
@cindex display interface configuration
|
@cindex VGA configuration
|
@cindex VGA configuration
|
@cindex @code{section vga}
|
@cindex @code{section vga}
|
@value{OR1KSIM} models a VGA interface to an external monitor. The
|
@value{OR1KSIM} models a VGA interface to an external monitor. The
|
VGA controller used in @value{OR1KSIM} is the component implemented at
|
VGA controller used in @value{OR1KSIM} is the component implemented at
|
OpenCores, and found in the top level CVS directory, @file{vga_lcd},
|
OpenCores, and found in the top level SVN directory, @file{vga_lcd},
|
with no support for the optional hardware cursors. It is described in
|
with no support for the optional hardware cursors. It is described in
|
the document @cite{VGA/LCD Core v2.0 Specifications} by Richard
|
the document @cite{VGA/LCD Core v2.0 Specifications} by Richard
|
Herveille, which can be found in the @file{doc} subdirectory. It is a
|
Herveille, which can be found in the @file{doc} subdirectory. It is a
|
memory mapped component, which resides on the main OpenRISC Wishbone
|
memory mapped component, which resides on the main OpenRISC Wishbone
|
data bus.
|
data bus.
|
| Line 2407... |
Line 2465... |
@cindex keyboard configuration
|
@cindex keyboard configuration
|
@cindex PS2 configuration
|
@cindex PS2 configuration
|
@cindex @code{section kb}
|
@cindex @code{section kb}
|
The PS2 interface provided by @value{OR1KSIM} is not documented. It
|
The PS2 interface provided by @value{OR1KSIM} is not documented. It
|
may be based on the PS2 project at OpenCores, and found in
|
may be based on the PS2 project at OpenCores, and found in
|
the top level CVS directory, @file{ps2}. However this project lacks
|
the top level SVN directory, @file{ps2}. However this project lacks
|
any documentation beyond its project webpage. Since most PS2
|
any documentation beyond its project webpage. Since most PS2
|
interfaces follow the Intel i8042 standard, this is presumably what is
|
interfaces follow the Intel i8042 standard, this is presumably what is
|
expected with this device.
|
expected with this device.
|
|
|
The implementation only provides for keyboard support, which is
|
The implementation only provides for keyboard support, which is
|
| Line 2474... |
Line 2532... |
@cindex disc interface configuration
|
@cindex disc interface configuration
|
@cindex ATA/ATAPI configuration
|
@cindex ATA/ATAPI configuration
|
@cindex @code{section ata}
|
@cindex @code{section ata}
|
The ATA/ATAPI disc controller used in @value{OR1KSIM} is the OCIDEC
|
The ATA/ATAPI disc controller used in @value{OR1KSIM} is the OCIDEC
|
(OpenCores IDE Controller) component implemented at OpenCores, and
|
(OpenCores IDE Controller) component implemented at OpenCores, and
|
found in the top level CVS directory, @file{ata}. It is described in
|
found in the top level SVN directory, @file{ata}. It is described in
|
the document @cite{ATA/ATAPI-5 Core Specification} by Richard
|
the document @cite{ATA/ATAPI-5 Core Specification} by Richard
|
Herveille, which can be found in the @file{doc} subdirectory. It is a
|
Herveille, which can be found in the @file{doc} subdirectory. It is a
|
memory mapped component, which resides on the main OpenRISC Wishbone
|
memory mapped component, which resides on the main OpenRISC Wishbone
|
data bus.
|
data bus.
|
|
|
