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Line 43... |
#include "sprs.h"
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#include "sprs.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "sched.h"
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#include "sched.h"
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/* FIXME: This ugly hack will be removed once the bus architecture gets written
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/* -------------------------------------------------------------------------- */
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*/
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/* Reset the PIC.
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struct pic pic_state_int = { 1, 1 };
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struct pic *pic_state = &pic_state_int;
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/* Reset. It initializes PIC registers. */
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Sets registers to consistent values. */
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/* -------------------------------------------------------------------------- */
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void
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void
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pic_reset (void)
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pic_reset (void)
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{
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{
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PRINTFQ ("Resetting PIC.\n");
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PRINTFQ ("Resetting PIC.\n");
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cpu_state.sprs[SPR_PICMR] = 0;
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cpu_state.sprs[SPR_PICMR] = config.pic.use_nmi ? 0x00000003 : 0x00000000;
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cpu_state.sprs[SPR_PICPR] = 0;
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cpu_state.sprs[SPR_PICSR] = 0x00000000;
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cpu_state.sprs[SPR_PICSR] = 0;
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}
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} /* pic_reset () */
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/* -------------------------------------------------------------------------- */
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/* Handle the reporting of an interrupt
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/* Handles the reporting of an interrupt if it had to be delayed */
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PIC interrupts are scheduled to take place after the current instruction
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has completed execution.
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@param[in] dat Data associated with the exception (not used) */
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/* -------------------------------------------------------------------------- */
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static void
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static void
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pic_rep_int (void *dat)
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pic_rep_int (void *dat)
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{
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{
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/* printf ("Handling interrupt PICSR: 0x%08x\n", cpu_state.sprs[SPR_PICSR]);
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*/
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if (cpu_state.sprs[SPR_PICSR])
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if (cpu_state.sprs[SPR_PICSR])
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{
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{
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except_handle (EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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except_handle (EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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}
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}
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}
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} /* pic_rep_int () */
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/* Called whenever interrupts get enabled */
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/* -------------------------------------------------------------------------- */
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/* Enable interrupts.
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Called whenever interrupts get enabled, or when PICMR is written.
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@todo Not sure if calling whenever PICMR is written is a good
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idea. However, so long as interrupts are properly cleared, it should
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not be a problem. */
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/* -------------------------------------------------------------------------- */
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void
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void
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pic_ints_en (void)
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pic_ints_en (void)
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{
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{
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if ((cpu_state.sprs[SPR_PICMR] & cpu_state.sprs[SPR_PICSR]))
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if ((cpu_state.sprs[SPR_PICMR] & cpu_state.sprs[SPR_PICSR]))
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{
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SCHED_ADD (pic_rep_int, NULL, 0);
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SCHED_ADD (pic_rep_int, NULL, 0);
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}
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}
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} /* pic_ints_en () */
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/* -------------------------------------------------------------------------- */
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/*!Assert an interrupt to the PIC
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OpenRISC supports both edge and level triggered interrupt. The only
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difference is how the interrupt is cleared. For edge triggered, it is by
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clearing the corresponding bit in PICSR. For level triggered it is by
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deasserting the interrupt line.
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/* Asserts interrupt to the PIC. */
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For integrated peripherals, these amount to the same thing (using
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/* WARNING: If this is called during a simulated instruction (ie. from a read/
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clear_interrupt ()). For external peripherals, the library provides two
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* write mem callback), the interrupt will be delivered after the instruction
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distinct interfaces.
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* has finished executeing */
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An interrupt disables any power management activity.
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We warn if an interrupt is received on a line that already has an interrupt
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pending.
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@note If this is called during a simulated instruction (ie. from a read/
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write mem callback), the interrupt will be delivered after the
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instruction has finished executing.
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@param[in] line The interrupt being asserted. */
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/* -------------------------------------------------------------------------- */
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void
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void
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report_interrupt (int line)
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report_interrupt (int line)
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{
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{
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uint32_t lmask = 1 << line;
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uint32_t lmask = 1 << line;
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/* printf ("Interrupt reported on line %d\n", line); */
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/* Disable doze and sleep mode */
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/* Disable doze and sleep mode */
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cpu_state.sprs[SPR_PMR] &= ~(SPR_PMR_DME | SPR_PMR_SME);
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cpu_state.sprs[SPR_PMR] &= ~(SPR_PMR_DME | SPR_PMR_SME);
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/* If PIC is disabled, don't set any register, just raise EXCEPT_INT */
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/* If PIC is disabled, don't set any register, just raise EXCEPT_INT */
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if (!config.pic.enabled)
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if (!config.pic.enabled)
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Line 139... |
if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
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if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
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except_handle (EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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except_handle (EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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return;
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return;
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}
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}
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/* We can't take another interrupt if the previous one has not been
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cleared. */
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if (cpu_state.sprs[SPR_PICSR] & lmask)
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if (cpu_state.sprs[SPR_PICSR] & lmask)
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{
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{
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/* Interrupt already signaled and pending */
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/* Interrupt already signaled and pending */
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fprintf (stderr, "Warning: Int line %d did not change state\n", line);
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PRINTF ("Warning: Int on line %d pending: ignored\n", line);
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return;
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return;
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}
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}
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cpu_state.sprs[SPR_PICSR] |= lmask;
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cpu_state.sprs[SPR_PICSR] |= lmask;
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if ((cpu_state.sprs[SPR_PICMR] & lmask) || line < 2)
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/* If we are enabled in the mask, and interrupts are globally enabled in the
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if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
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SR, schedule the interrupt to take place after the next instruction. */
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if ((cpu_state.sprs[SPR_PICMR] & lmask) &&
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(cpu_state.sprs[SPR_SR] & SPR_SR_IEE))
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{
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/* printf ("Scheduling interrupt on line %d\n", line); */
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SCHED_ADD (pic_rep_int, NULL, 0);
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SCHED_ADD (pic_rep_int, NULL, 0);
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}
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}
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} /* report_interrupt () */
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/* -------------------------------------------------------------------------- */
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/* Clear an interrupt on a PIC line.
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Logically this is different for a level sensitive interrupt (it lowers the
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input line) and an edge sensitive interrupt (it clears the PICSR bit).
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However within Or1ksim, these are implemented through the same operation -
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clearing the bit in PICSR.
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/* Clears an int on a pic line */
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@param[in] line The interrupt being cleared. */
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/* -------------------------------------------------------------------------- */
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void
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void
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clear_interrupt (int line)
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clear_interrupt (int line)
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{
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{
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/* When level triggered, clear corresponding bit in PICSR */
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if (!config.pic.edge_trigger)
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{
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cpu_state.sprs[SPR_PICSR] &= ~(1 << line);
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cpu_state.sprs[SPR_PICSR] &= ~(1 << line);
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}
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}
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} /* clear_interrupt */
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/*----------------------------------------------------[ PIC configuration ]---*/
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/*----------------------------------------------------[ PIC configuration ]---*/
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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Line 225... |
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} /* pic_edge_trigger() */
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} /* pic_edge_trigger() */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Enable or disable non-maskable interrupts
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@param[in] val The value to use
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@param[in] dat The config data structure (not used here) */
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/*---------------------------------------------------------------------------*/
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static void
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pic_use_nmi (union param_val val,
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void *dat)
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{
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config.pic.use_nmi = val.int_val;
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} /* pic_use_nmi() */
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/*---------------------------------------------------------------------------*/
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/*!Initialize a new interrupt controller configuration
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/*!Initialize a new interrupt controller configuration
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ALL parameters are set explicitly to default values in init_defconfig() */
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ALL parameters are set explicitly to default values in init_defconfig() */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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void
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void
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| Line 178... |
Line 251... |
{
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{
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struct config_section *sec = reg_config_sec ("pic", NULL, NULL);
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struct config_section *sec = reg_config_sec ("pic", NULL, NULL);
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reg_config_param (sec, "enabled", PARAMT_INT, pic_enabled);
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reg_config_param (sec, "enabled", PARAMT_INT, pic_enabled);
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reg_config_param (sec, "edge_trigger", PARAMT_INT, pic_edge_trigger);
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reg_config_param (sec, "edge_trigger", PARAMT_INT, pic_edge_trigger);
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reg_config_param (sec, "use_nmi", PARAMT_INT, pic_use_nmi);
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} /* reg_pic_sec() */
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} /* reg_pic_sec() */
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No newline at end of file
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No newline at end of file
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