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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [libsim.tests/] [default.cfg] - Diff between revs 90 and 98

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Rev 90 Rev 98
Line 49... Line 49...
  size = 0x00200000
  size = 0x00200000
  delayr = 2
  delayr = 2
  delayw = 4
  delayw = 4
end
end
 
 
 
/* High memory for testing */
 
section memory
 
  /*random_seed = 12345
 
  type = random*/
 
  pattern = 0x00
 
  type = unknown /* Fastest */
 
 
 
  name = "RAM"
 
  ce = 2
 
  mc = 0
 
  baseaddr = 0xffe00000
 
  size = 0x00200000
 
  delayr = 2
 
  delayw = 4
 
end
 
 
section immu
section immu
  enabled = 1
  enabled = 1
  nsets = 64
  nsets = 64
  nways = 1
  nways = 1
  ustates = 2
  ustates = 2
Line 81... Line 97...
  nways = 1
  nways = 1
  ustates = 2
  ustates = 2
  blocksize = 16
  blocksize = 16
end
end
 
 
 
/* Set the CPU to take vectors at 0xf0000000 */
section cpu
section cpu
  ver =   0x12
  ver =   0x12
  rev = 0x0001
  rev = 0x0001
  /* upr = */
  /* upr = */
 
  sr = 0xc001
  superscalar = 0
  superscalar = 0
  hazards = 0
  hazards = 0
  dependstats = 0
  dependstats = 0
end
end
 
 
Line 111... Line 129...
  exe_log = 0
  exe_log = 0
  exe_log_type = software
  exe_log_type = software
  exe_log_fn = "executed.log"
  exe_log_fn = "executed.log"
end
end
 
 
 
/* Memory instead of MC. Stops write errors when the startup code tries to
 
   access a non-existent MC */
 
section memory
 
  /*random_seed = 12345
 
  type = random*/
 
  pattern = 0x00
 
  type = unknown /* Fastest */
 
 
 
  name = "MC shadow"
 
  baseaddr = 0x93000000
 
  size     = 0x00000080
 
  delayr = 2
 
  delayw = 4
 
end
 
 
 
/* Disabled */
section mc
section mc
  enabled = 1
  enabled = 0
  baseaddr = 0x93000000
  baseaddr = 0x93000000
  POC = 0x00000008                 /* Power on configuration register */
  POC = 0x00000008                 /* Power on configuration register */
  index = 0
  index = 0
end
end
 
 

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