URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [uos/] [except-or32.S] - Diff between revs 346 and 787

Rev 346	Rev 787
Line 198...	Line 198...
`* Reset Exception handler`	`* Reset Exception handler`
`*/`	`*/`
`.org 0x100`	`.org 0x100`
`reset_vector:`	`reset_vector:`

	`// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,`
	`// and indeed it is not when simulating the or1200 Verilog core.`
	`l.andi r0,r0,0x0`

`l.movhi r3,hi(MC_BASE_ADDR)`	`l.movhi r3,hi(MC_BASE_ADDR)`
`l.ori r3,r3,lo(MC_BASE_ADDR)`	`l.ori r3,r3,lo(MC_BASE_ADDR)`

`l.addi r4,r3,MC_CSC(0)`	`l.addi r4,r3,MC_CSC(0)`
`l.movhi r5,hi(FLASH_BASE_ADDR)`	`l.movhi r5,hi(FLASH_BASE_ADDR)`