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| Rev 40 |
Rev 46 |
| Line 96... |
Line 96... |
integer jtag_instn_val;
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integer jtag_instn_val;
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integer set_chain_val;
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integer set_chain_val;
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reg [1:0] cpu_ctrl_val; // two important bits for the ctrl reg
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reg [1:0] cpu_ctrl_val; // two important bits for the ctrl reg
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reg [31:0] cmd_adr;
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reg [31:0] cmd_adr;
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reg [31:0] cmd_size;
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reg [31:0] cmd_data;
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reg [31:0] cmd_data;
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initial
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initial
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begin
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begin
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| Line 226... |
Line 227... |
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$return_command_data(cmd_data);
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$return_command_data(cmd_data);
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end
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end
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`CMD_WB_WR32 :
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`CMD_WB_WR :
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begin
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begin
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$get_command_address(cmd_adr);
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$get_command_address(cmd_adr);
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$get_command_data(cmd_size);
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$get_command_data(cmd_data);
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$get_command_data(cmd_data);
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case (cmd_size)
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4 :
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begin
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wb_write_32(cmd_data, cmd_adr, 16'h3);
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wb_write_32(cmd_data, cmd_adr, 16'h3);
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end
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2 :
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begin
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wb_write_16(cmd_data[15:0], cmd_adr, 16'h1);
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end
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1 :
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begin
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wb_write_8(cmd_data[7:0], cmd_adr, 16'h0);
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end
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default:
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begin
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$display("* vpi_debug_module: CMD_WB_WR size incorrect: %d\n", cmd_size);
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end
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endcase // case (cmd_size)
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end
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end
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`CMD_WB_RD32 :
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`CMD_WB_RD32 :
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begin
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begin
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