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Line 6... |
#### - Julius Baxter, julius@opencores.org ####
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#### - Julius Baxter, julius@opencores.org ####
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#### ####
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#### ####
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#### ####
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#### ####
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######################################################################
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######################################################################
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#### ####
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#### ####
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#### Copyright (C) 2009,2010 Authors and OPENCORES.ORG ####
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#### Copyright (C) 2009,2010,2011 Authors and OPENCORES.ORG ####
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#### ####
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#### ####
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#### This source file may be used and distributed without ####
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#### This source file may be used and distributed without ####
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#### restriction provided that this copyright statement is not ####
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#### restriction provided that this copyright statement is not ####
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#### removed from the file and that any derivative work contains ####
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#### removed from the file and that any derivative work contains ####
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#### the original copyright notice and the associated disclaimer. ####
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#### the original copyright notice and the associated disclaimer. ####
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######################################################################
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######################################################################
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# Name of the directory we're currently in
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# Name of the directory we're currently in
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CUR_DIR=$(shell pwd)
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CUR_DIR=$(shell pwd)
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# We don't want the usbhostslave module to be pulled in during synthesis because
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# we haven't copied the headers to our RTL director
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#COMMON_VERILOG_MODULES_EXCLUDE+= usbhostslave
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# The root path of the board build
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# The root path of the board build
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BOARD_DIR ?=$(CUR_DIR)/../../..
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BOARD_ROOT ?=$(CUR_DIR)/../../..
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PROJECT_ROOT=$(BOARD_DIR)/../../..
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include $(BOARD_ROOT)/Makefile.inc
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DESIGN_NAME ?=orpsoc
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RTL_TOP ?=$(DESIGN_NAME)_top
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RTL_TOP ?=$(DESIGN_NAME)_top
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SYN_DIR=$(BOARD_DIR)/syn/xst
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SYN_RUN_DIR=$(BOARD_SYN_DIR)/run
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SYN_RUN_DIR=$(SYN_DIR)/run
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# Paths to other important parts of this test suite
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COMMON_RTL_DIR = $(PROJECT_ROOT)/rtl
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COMMON_RTL_VERILOG_DIR = $(COMMON_RTL_DIR)/verilog
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#COMMON_RTL_VHDL_DIR = $(COMMON_RTL_DIR)/vhdl
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BOARD_RTL_DIR=$(BOARD_DIR)/rtl
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BOARD_RTL_VERILOG_DIR=$(BOARD_RTL_DIR)/verilog
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# Only 1 include path for board builds - their own!
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BOARD_RTL_VERILOG_INCLUDE_DIR=$(BOARD_RTL_VERILOG_DIR)/include
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BOARD_DESIGN_VERILOG_DEFINES=$(BOARD_RTL_VERILOG_INCLUDE_DIR)/$(DESIGN_NAME)-defines.v
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#BOARD_RTL_VHDL_DIR = $(BOARD_RTL_DIR)/vhdl
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BACKEND_DIR=$(BOARD_DIR)/backend
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BACKEND_BIN_DIR=$(BACKEND_DIR)/bin
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# Set V=1 when calling make to enable verbose output
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# mainly for debugging purposes.
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ifeq ($(V), 1)
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Q=
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else
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Q ?=@
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endif
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DEFINES_FILE_CUTOFF=$(shell grep -n "end of included module defines" $(BOARD_DESIGN_VERILOG_DEFINES) | cut -d ':' -f 1)
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DESIGN_DEFINES=$(shell cat $(BOARD_DESIGN_VERILOG_DEFINES) | sed s://.*::g | sed s:\`:\#:g | sed 's:^[ ]*::' | awk '{print};/^\#define/{printf "_%s=%s\n",$$2,$$2}' | grep -v PERIOD | cpp -P | sed s:^_::g | sed s:=$$::g )
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# Rule to look at what defines are being extracted from main file
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print-defines:
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@echo; echo "\t### Design defines ###"; echo
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@echo "\tParsing "$(BOARD_DESIGN_VERILOG_DEFINES)" and exporting:"
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@echo $(DESIGN_DEFINES)
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# Backend tool path
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# Check that the XILINX_PATH variable is set
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ifeq ($(XILINX_PATH),)
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$(error XILINX_PATH environment variable not set. Set it and rerun)
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endif
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XILINX_SETTINGS_SCRIPT=$(XILINX_PATH)/settings32.sh
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XILINX_SETTINGS_SCRIPT_EXISTS=$(shell if [ -e $(XILINX_SETTINGS_SCRIPT) ]; then echo 1; else echo 0; fi)
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ifeq ($(XILINX_SETTINGS_SCRIPT_EXISTS),0)
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$(error XILINX_PATH variable not set correctly. Cannot find $$XILINX_PATH/settings32.sh)
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endif
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#
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# Verilog DUT source variables
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#
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# First we get a list of modules in the RTL path of the board's path.
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# Next we check which modules not in the board's RTL path are in the root RTL
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# path (modules which can be commonly instantiated, but over which board
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# build-specific versions take precedence.)
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# Paths under board/***/rtl/verilog we wish to exclude when getting modules
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BOARD_VERILOG_MODULES_EXCLUDE= include
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BOARD_VERILOG_MODULES_DIR_LIST=$(shell ls $(BOARD_RTL_VERILOG_DIR))
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# Apply exclude to list of modules
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BOARD_RTL_VERILOG_MODULES=$(filter-out $(BOARD_VERILOG_MODULES_EXCLUDE),$(BOARD_VERILOG_MODULES_DIR_LIST))
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# Rule for debugging this script
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print-board-modules:
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$(Q)echo echo; echo "\t### Board verilog modules ###"; echo;
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$(Q)echo $(BOARD_RTL_VERILOG_MODULES)
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# Now get list of modules that we don't have a version of in the board path
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# List others that cause clahes (ie. source listed, due to utterly pathetic XST
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# not supporting ability to specify search paths, and requiring includes but
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# not used in this board build, hence its includes are not there and result
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# in error.)
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COMMON_VERILOG_MODULES_EXCLUDE= include usbhostslave
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COMMON_VERILOG_MODULES_EXCLUDE += $(BOARD_RTL_VERILOG_MODULES)
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COMMON_RTL_VERILOG_MODULES_DIR_LIST=$(shell ls $(COMMON_RTL_VERILOG_DIR))
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COMMON_RTL_VERILOG_MODULES=$(filter-out $(COMMON_VERILOG_MODULES_EXCLUDE), $(COMMON_RTL_VERILOG_MODULES_DIR_LIST))
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# Rule for debugging this script
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print-common-modules-exclude:
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$(Q)echo echo; echo "\t### Common verilog modules being excluded due to board versions ###"; echo;
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$(Q)echo "$(COMMON_VERILOG_MODULES_EXCLUDE)"
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print-common-modules:
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$(Q)echo echo; echo "\t### Verilog modules from common RTL dir ###"; echo
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$(Q)echo $(COMMON_RTL_VERILOG_MODULES)
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# List of verilog source files (only .v files!)
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# Board RTL modules first
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VERILOG_SRC_PATHS=$(addprefix $(BOARD_RTL_VERILOG_DIR)/,$(BOARD_RTL_VERILOG_MODULES))
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VERILOG_SRC_PATHS +=$(addprefix $(COMMON_RTL_VERILOG_DIR)/,$(COMMON_RTL_VERILOG_MODULES))
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RTL_VERILOG_SRC=$(shell for modulepath in $(VERILOG_SRC_PATHS); do \
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if [ -d $$modulepath ]; then \
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ls $$modulepath/*.v; \
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fi; done)
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# List of verilog includes from board RTL path - only for rule sensitivity
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RTL_VERILOG_INCLUDES=$(shell ls $(BOARD_RTL_VERILOG_INCLUDE_DIR)/*.*)
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#
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# VHDL DUT source variables
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#
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# VHDL modules
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#RTL_VHDL_MODULES=$(shell ls $(RTL_VHDL_DIR))
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# VHDL sources
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#RTL_VHDL_SRC=$(shell for module in $(RTL_VHDL_MODULES); do if [ -d $(RTL_VHDL_DIR)/$$module ]; then ls $(RTL_VHDL_DIR)/$$module/*.vhd; fi; done)
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#
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# Dynamically created files included by different parts of the defines
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#
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BOARD_SW_DIR=$(BOARD_DIR)/sw
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# BootROM code, which generates a verilog array select values
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BOOTROM_FILE=bootrom.v
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BOARD_BOOTROM_SW_DIR=$(BOARD_SW_DIR)/bootrom
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BOOTROM_VERILOG=$(BOARD_BOOTROM_SW_DIR)/$(BOOTROM_FILE)
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# Export BOARD for the software makefiles
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BOARD=xilinx/ml501
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export BOARD
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bootrom: $(BOOTROM_VERILOG)
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$(BOOTROM_VERILOG):
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$(MAKE) -C $(BOARD_BOOTROM_SW_DIR) $(BOOTROM_FILE)
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TIMESCALE_FILE=timescale.v
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TIMESCALE_FILE=timescale.v
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SYNDIR_TIMESCALE_FILE=$(SYN_RUN_DIR)/$(TIMESCALE_FILE)
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SYNDIR_TIMESCALE_FILE=$(SYN_RUN_DIR)/$(TIMESCALE_FILE)
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$(SYNDIR_TIMESCALE_FILE):
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$(SYNDIR_TIMESCALE_FILE):
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$(Q)echo "" > $@
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$(Q)echo "" > $@
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| Line 181... |
Line 63... |
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GENERATED_DEFINES = $(BOOTROM_VERILOG)
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GENERATED_DEFINES = $(BOOTROM_VERILOG)
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GENERATED_DEFINES += $(SYNDIR_TIMESCALE_FILE)
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GENERATED_DEFINES += $(SYNDIR_TIMESCALE_FILE)
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GENERATED_DEFINES += $(SYNDIR_SYN_VERILOG_DEFINES)
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GENERATED_DEFINES += $(SYNDIR_SYN_VERILOG_DEFINES)
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FPGA_PART ?=xc5vlx50-ff676-1
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FPGA_PART ?=xc5vlx50-ff676-1
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OPT_MODE ?=Speed
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OPT_MODE ?=Speed
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OPT_LEVEL ?=2
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OPT_LEVEL ?=2
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|
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XILINX_FLAGS ?=-intstyle silent
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XILINX_FLAGS ?=-intstyle silent
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XILINX_XST_FLAGS ?= -power NO -glob_opt AllClockNets -write_timing_constraints NO -cross_clock_analysis NO -slice_utilization_ratio 100 -bram_utilization_ratio 100 -dsp_utilization_ratio 100 -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -rom_style Auto -auto_bram_packing NO -mux_extract YES -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -resource_sharing YES -async_to_sync NO -use_dsp48 auto -iobuf YES -max_fanout 100000 -bufg 32 -register_duplication YES -equivalent_register_removal YES -register_balancing No -slice_packing YES -optimize_primitives NO -use_clock_enable Auto -use_sync_set Auto -use_sync_reset Auto -iob Auto -slice_utilization_ratio_maxmargin 5
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XILINX_XST_FLAGS ?= -power NO -glob_opt AllClockNets -write_timing_constraints NO -cross_clock_analysis NO -slice_utilization_ratio 100 -bram_utilization_ratio 100 -dsp_utilization_ratio 100 -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -rom_style Auto -auto_bram_packing NO -mux_extract YES -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -resource_sharing YES -async_to_sync NO -use_dsp48 auto -iobuf YES -max_fanout 100000 -bufg 32 -register_duplication YES -equivalent_register_removal YES -register_balancing No -slice_packing YES -optimize_primitives NO -use_clock_enable Auto -use_sync_set Auto -use_sync_reset Auto -iob Auto -slice_utilization_ratio_maxmargin 5
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|
|
XCF_FILE=$(DESIGN_NAME).xcf
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XCF_FILE=$(DESIGN_NAME).xcf
|
XST_FILE=$(DESIGN_NAME).xst
|
XST_FILE=$(DESIGN_NAME).xst
|
| Line 232... |
Line 112... |
# $(Q)echo "elaborate " >> $@
|
# $(Q)echo "elaborate " >> $@
|
# $(Q)echo -n "-vlgpath \"" >> $@
|
# $(Q)echo -n "-vlgpath \"" >> $@
|
# option missing from XST - wtf?! $(Q)for vlogpath in $(VERILOG_SRC_PATHS); do \
|
# option missing from XST - wtf?! $(Q)for vlogpath in $(VERILOG_SRC_PATHS); do \
|
echo -n $$vlogpath" "; done >> $@
|
echo -n $$vlogpath" "; done >> $@
|
# $(Q)echo "\"" >> $@
|
# $(Q)echo "\"" >> $@
|
$(Q)echo "-vlgincdir { "$(BOARD_RTL_VERILOG_INCLUDE_DIR)" "$(BOARD_BOOTROM_SW_DIR) " }" >> $@
|
# Give board then common verilog include paths, hoping xst does a sensible thing
|
|
# and searches them in order.
|
|
$(Q)echo "-vlgincdir { "$(BOARD_RTL_VERILOG_INCLUDE_DIR)" "$(COMMON_RTL_VERILOG_DIR)/include" "$(BOOTROM_SW_DIR) " }" >> $@
|
$(Q)echo >> $@
|
$(Q)echo >> $@
|
|
|
# Generate Xilinx project (.prj) file
|
# Generate Xilinx project (.prj) file
|
$(PRJ_FILE): $(RTL_VERILOG_SRC)
|
$(PRJ_FILE): $(RTL_VERILOG_SRC)
|
$(Q)echo; echo "\t#### Generating Xilinx PRJ file ####";
|
$(Q)echo; echo "\t#### Generating Xilinx PRJ file ####";
|
