| Line 435... |
Line 435... |
wire RxWordAcc;
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wire RxWordAcc;
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wire RxHalfAcc;
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wire RxHalfAcc;
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wire RxByteAcc;
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wire RxByteAcc;
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wire ResetTxBDReady;
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reg BlockingTxStatusWrite_sync1;
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reg BlockingTxStatusWrite_sync2;
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reg BlockingTxStatusWrite_sync3;
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reg cyc_cleared;
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reg IncrTxPointer;
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reg [3:0] RxByteSel;
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wire MasterAccessFinished;
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reg LatchValidBytes;
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reg LatchValidBytes_q;
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// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
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reg ReadTxDataFromFifo_sync1;
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reg ReadTxDataFromFifo_sync2;
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reg ReadTxDataFromFifo_sync3;
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reg ReadTxDataFromFifo_syncb1;
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reg ReadTxDataFromFifo_syncb2;
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reg ReadTxDataFromFifo_syncb3;
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reg RxAbortSync1;
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reg RxAbortSync2;
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reg RxAbortSync3;
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reg RxAbortSync4;
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reg RxAbortSyncb1;
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reg RxAbortSyncb2;
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reg RxEnableWindow;
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wire SetWriteRxDataToFifo;
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reg WriteRxDataToFifoSync1;
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reg WriteRxDataToFifoSync2;
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reg WriteRxDataToFifoSync3;
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wire WriteRxDataToFifo_wb;
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// Receive fifo selection register - JB
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reg [3:0] rx_shift_ended_wb_shr;
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reg rx_ethside_fifo_sel /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */;
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reg rx_wbside_fifo_sel /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */;
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reg rx_discard_packet;
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reg LatchedRxStartFrm;
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reg SyncRxStartFrm;
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reg SyncRxStartFrm_q;
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reg SyncRxStartFrm_q2;
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wire RxFifoReset;
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wire [31:0] rx_fifo0_data_out;
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wire rx_fifo0_write;
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wire rx_fifo0_read;
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wire rx_fifo0_clear;
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wire rx_fifo0_full;
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wire rx_fifo0_afull;
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wire rx_fifo0_empty;
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wire rx_fifo0_aempty;
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wire [31:0] rx_fifo1_data_out;
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wire rx_fifo1_write;
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wire rx_fifo1_read;
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wire rx_fifo1_clear;
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wire rx_fifo1_full;
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wire rx_fifo1_afull;
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wire rx_fifo1_empty;
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wire rx_fifo1_aempty;
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wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo0_cnt;
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wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo1_cnt;
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wire TxError;
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wire RxError;
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wire write_rx_data_to_memory_wait;
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wire write_rx_data_to_memory_go;
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reg RxStatusWriteLatched;
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reg RxStatusWriteLatched_sync1;
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reg RxStatusWriteLatched_sync2;
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reg RxStatusWriteLatched_syncb1;
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reg RxStatusWriteLatched_syncb2;
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reg busy_wb;
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reg overflow_bug_reset;
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// Fix bug when overflow causes things to become a bit confused
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always @ (posedge WB_CLK_I)
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if (Reset)
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overflow_bug_reset <= 0;
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else
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overflow_bug_reset <= (rx_fifo1_empty & rx_fifo0_empty &
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!RxEnableWindow & !rx_wb_writeback_finished &
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!rx_wb_last_writes & RxEn & RxEn_q &
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(rx_ethside_fifo_sel != rx_wbside_fifo_sel));
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always @(posedge overflow_bug_reset)
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$display("%t: %m overflow_bug_reset posedge",$time);
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`ifdef ETH_WISHBONE_B3
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`ifdef ETH_WISHBONE_B3
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`ifndef BURST_4BEAT
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`ifndef BURST_4BEAT
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assign m_wb_bte_o = 2'b00; // Linear burst
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assign m_wb_bte_o = 2'b00; // Linear burst
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`endif
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`endif
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`endif
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`endif
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| Line 611... |
Line 716... |
else
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else
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if(TxUsedData)
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if(TxUsedData)
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Flop <= ~Flop;
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Flop <= ~Flop;
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end
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end
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wire ResetTxBDReady;
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assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
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assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
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// Latching READY status of the Tx buffer descriptor
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// Latching READY status of the Tx buffer descriptor
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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| Line 683... |
Line 787... |
if(TxStatusWrite)
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if(TxStatusWrite)
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BlockingTxStatusWrite <= 1'b1;
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BlockingTxStatusWrite <= 1'b1;
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end
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end
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reg BlockingTxStatusWrite_sync1;
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reg BlockingTxStatusWrite_sync2;
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reg BlockingTxStatusWrite_sync3;
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// Synchronizing BlockingTxStatusWrite to MTxClk
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// Synchronizing BlockingTxStatusWrite to MTxClk
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always @ (posedge MTxClk or posedge Reset)
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always @ (posedge MTxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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BlockingTxStatusWrite_sync1 <= 1'b0;
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BlockingTxStatusWrite_sync1 <= 1'b0;
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| Line 766... |
Line 866... |
else
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else
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if(MasterWbTX & m_wb_ack_i)
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if(MasterWbTX & m_wb_ack_i)
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begin
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begin
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if(TxLengthLt4)
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if(TxLengthLt4)
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TxLength <= 16'h0;
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TxLength <= 16'h0;
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else
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else if(TxPointerLSB_rst==2'h0)
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if(TxPointerLSB_rst==2'h0)
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TxLength <= TxLength - 16'd4; // Length is subtracted at
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TxLength <= TxLength - 16'd4; // Length is subtracted at
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// the data request
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// the data request
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else
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else if(TxPointerLSB_rst==2'h1)
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if(TxPointerLSB_rst==2'h1)
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TxLength <= TxLength - 16'd3; // Length is subtracted
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TxLength <= TxLength - 16'd3; // Length is subtracted
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// at the data request
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// at the data request
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else
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else if(TxPointerLSB_rst==2'h2)
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if(TxPointerLSB_rst==2'h2)
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TxLength <= TxLength - 16'd2; // Length is subtracted
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TxLength <= TxLength - 16'd2; // Length is subtracted
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// at the data request
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// at the data request
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else
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else if(TxPointerLSB_rst==2'h3)
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if(TxPointerLSB_rst==2'h3)
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TxLength <= TxLength - 16'd1; // Length is subtracted
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TxLength <= TxLength - 16'd1; // Length is subtracted
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// at the data request
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// at the data request
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end
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end
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end
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end
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//Latching length from the buffer descriptor;
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//Latching length from the buffer descriptor;
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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LatchedTxLength <= 16'h0;
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LatchedTxLength <= 16'h0;
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| Line 800... |
Line 894... |
end
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end
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assign TxLengthEq0 = TxLength == 0;
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assign TxLengthEq0 = TxLength == 0;
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assign TxLengthLt4 = TxLength < 4;
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assign TxLengthLt4 = TxLength < 4;
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reg cyc_cleared;
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reg IncrTxPointer;
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// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are
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// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are
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// latched because TxPointerMSB is only used for word-aligned accesses.
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// latched because TxPointerMSB is only used for word-aligned accesses.
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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| Line 852... |
Line 943... |
if(MasterWbTX & m_wb_ack_i)
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if(MasterWbTX & m_wb_ack_i)
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TxPointerLSB_rst[1:0] <= 0;
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TxPointerLSB_rst[1:0] <= 0;
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end
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end
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reg [3:0] RxByteSel;
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wire MasterAccessFinished;
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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BlockingIncrementTxPointer <= 0;
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BlockingIncrementTxPointer <= 0;
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else
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else
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| Line 1342... |
Line 1429... |
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// Marks which bytes are valid within the word.
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// Marks which bytes are valid within the word.
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assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
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assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
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reg LatchValidBytes;
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reg LatchValidBytes_q;
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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LatchValidBytes <= 1'b0;
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LatchValidBytes <= 1'b0;
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else
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else
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| Line 1390... |
Line 1474... |
assign RxIRQEn = RxStatus[14];
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assign RxIRQEn = RxStatus[14];
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assign WrapRxStatusBit = RxStatus[13];
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assign WrapRxStatusBit = RxStatus[13];
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// Temporary Tx and Rx buffer descriptor address
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// Temporary Tx and Rx buffer descriptor address
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assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1) ; // Tx BD increment or wrap (last BD)
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assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} &
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(TxBDAddress + 1) ; // Tx BD increment or wrap
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// (last BD)
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assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
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assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
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{7{~WrapRxStatusBit}} & (RxBDAddress + 1) ; // Using next Rx BD (incremenrement address)
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{7{~WrapRxStatusBit}} & (RxBDAddress + 1) ; // Using next Rx BD (incremenrement address)
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| Line 1744... |
Line 1830... |
if(TxUsedData & Flop)
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if(TxUsedData & Flop)
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TxByteCnt <= TxByteCnt + 1'b1;
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TxByteCnt <= TxByteCnt + 1'b1;
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end
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end
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// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
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reg ReadTxDataFromFifo_sync1;
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reg ReadTxDataFromFifo_sync2;
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reg ReadTxDataFromFifo_sync3;
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reg ReadTxDataFromFifo_syncb1;
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reg ReadTxDataFromFifo_syncb2;
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reg ReadTxDataFromFifo_syncb3;
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always @ (posedge MTxClk or posedge Reset)
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always @ (posedge MTxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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ReadTxDataFromFifo_tck <= 1'b0;
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ReadTxDataFromFifo_tck <= 1'b0;
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else
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else
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| Line 1875... |
Line 1952... |
else
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else
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TxAbort_wb <= TxAbortSync1;
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TxAbort_wb <= TxAbortSync1;
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end
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end
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reg RxAbortSync1;
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reg RxAbortSync2;
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reg RxAbortSync3;
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reg RxAbortSync4;
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reg RxAbortSyncb1;
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reg RxAbortSyncb2;
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assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 |
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assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 |
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r_RxEn & ~r_RxEn_q;
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r_RxEn & ~r_RxEn_q;
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// Reading the Rx buffer descriptor
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// Reading the Rx buffer descriptor
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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| Line 1958... |
Line 2028... |
// RxBDOK generation
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// RxBDOK generation
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxBDOK <= 1'b0;
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RxBDOK <= 1'b0;
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else
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else if(rx_wb_writeback_finished | RxAbortSync2 & ~RxAbortSync3 |
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if(rx_wb_writeback_finished | RxAbortSync2 & ~RxAbortSync3 |
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~r_RxEn & r_RxEn_q)
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~r_RxEn & r_RxEn_q)
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RxBDOK <= 1'b0;
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RxBDOK <= 1'b0;
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else
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else if(RxBDReady)
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if(RxBDReady)
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RxBDOK <= 1'b1;
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RxBDOK <= 1'b1;
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end
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end
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// Reading Rx BD pointer
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// Reading Rx BD pointer
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assign StartRxPointerRead = RxBDRead & RxBDReady;
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assign StartRxPointerRead = RxBDRead & RxBDReady;
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| Line 2031... |
Line 2099... |
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxEn_needed <= 1'b0;
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RxEn_needed <= 1'b0;
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else
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else if(/*~RxReady &*/ r_RxEn & WbEn & ~WbEn_q)
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if(/*~RxReady &*/ r_RxEn & WbEn & ~WbEn_q)
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RxEn_needed <= 1'b1;
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RxEn_needed <= 1'b1;
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else
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else if(RxPointerRead & RxEn & RxEn_q)
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if(RxPointerRead & RxEn & RxEn_q)
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RxEn_needed <= 1'b0;
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RxEn_needed <= 1'b0;
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end
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end
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// Reception status is written back to the buffer descriptor after the end
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// Reception status is written back to the buffer descriptor after the end
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// of frame is detected.
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// of frame is detected.
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assign RxStatusWrite = rx_wb_writeback_finished & RxEn & RxEn_q;
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assign RxStatusWrite = rx_wb_writeback_finished & RxEn & RxEn_q;
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reg RxEnableWindow;
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// Indicating that last byte is being reveived
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// Indicating that last byte is being reveived
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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LastByteIn <= 1'b0;
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LastByteIn <= 1'b0;
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| Line 2144... |
Line 2208... |
2'h3: RxDataLatched1 <= RxDataLatched1;
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2'h3: RxDataLatched1 <= RxDataLatched1;
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endcase
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endcase
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end
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end
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end
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end
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wire SetWriteRxDataToFifo;
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// Assembling data that will be written to the rx_fifo
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// Assembling data that will be written to the rx_fifo
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
|
if(Reset)
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RxDataLatched2 <= 32'h0;
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RxDataLatched2 <= 32'h0;
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| Line 2167... |
Line 2229... |
3 : RxDataLatched2 <= {RxDataLatched1[31:8], 8'h0};
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3 : RxDataLatched2 <= {RxDataLatched1[31:8], 8'h0};
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endcase
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endcase
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end
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end
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reg WriteRxDataToFifoSync1;
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reg WriteRxDataToFifoSync2;
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reg WriteRxDataToFifoSync3;
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// Indicating start of the reception process
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// Indicating start of the reception process
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assign SetWriteRxDataToFifo = (RxValid & ~RxStartFrm &
|
assign SetWriteRxDataToFifo = (RxValid & ~RxStartFrm &
|
RxEnableWindow & (&RxByteCnt))
|
RxEnableWindow & (&RxByteCnt))
|
/*| (RxValid & RxStartFrm &
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/*| (RxValid & RxStartFrm &
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(&RxPointerLSB_rst)) */
|
(&RxPointerLSB_rst)) */
|
| Line 2220... |
Line 2277... |
WriteRxDataToFifoSync3 <= 1'b0;
|
WriteRxDataToFifoSync3 <= 1'b0;
|
else
|
else
|
WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2;
|
WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2;
|
end
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end
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|
|
wire WriteRxDataToFifo_wb;
|
|
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 &
|
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 &
|
~WriteRxDataToFifoSync3;
|
~WriteRxDataToFifoSync3;
|
// Receive fifo selection register - JB
|
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reg [3:0] rx_shift_ended_wb_shr;
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reg rx_ethside_fifo_sel /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */;
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// Signal to indicate data in current buffer should be discarded as we had
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reg rx_wbside_fifo_sel /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */;
|
// no open buffer for it.
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// Goes high when rx_wb_last_writes goes off and we still haven't gotten a
|
|
// RX buffer for it.
|
|
always @(posedge WB_CLK_I)
|
|
if (Reset)
|
|
rx_discard_packet <= 0;
|
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else if (rx_shift_ended_wb_shr[3:2] == 2'b01)
|
|
rx_discard_packet <= 0;
|
|
else if (rx_wb_last_writes & RxBDRead)
|
|
rx_discard_packet <= 1;
|
|
|
|
|
// Shift in this - our detection of end of data RX
|
// Shift in this - our detection of end of data RX
|
always @(posedge WB_CLK_I)
|
always @(posedge WB_CLK_I)
|
rx_shift_ended_wb_shr <= {rx_shift_ended_wb_shr[2:0],
|
rx_shift_ended_wb_shr <= {rx_shift_ended_wb_shr[2:0],
|
ShiftEndedSync1 & ~ShiftEndedSync2};
|
ShiftEndedSync1 & ~ShiftEndedSync2};
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
if(Reset)
|
if(Reset)
|
rx_ethside_fifo_sel <= 0;
|
rx_ethside_fifo_sel <= 0;
|
else
|
else if (rx_discard_packet | overflow_bug_reset)
|
if(rx_shift_ended_wb_shr[3:2] == 2'b01)
|
rx_ethside_fifo_sel <= 0;
|
|
else if(rx_shift_ended_wb_shr[3:2] == 2'b01 & !rx_discard_packet)
|
// Switch over whenever we've finished receiving last frame's data
|
// Switch over whenever we've finished receiving last frame's data
|
rx_ethside_fifo_sel <= ~rx_ethside_fifo_sel;
|
rx_ethside_fifo_sel <= ~rx_ethside_fifo_sel;
|
|
|
// Wishbone side looks at other FIFO when we write back the status of this
|
// Wishbone side looks at other FIFO when we write back the status of this
|
// received frame
|
// received frame
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
if(Reset)
|
if(Reset)
|
rx_wbside_fifo_sel <= 0;
|
rx_wbside_fifo_sel <= 0;
|
else
|
else if (rx_discard_packet | overflow_bug_reset)
|
if(rx_wb_writeback_finished & RxEn & RxEn_q)
|
rx_wbside_fifo_sel <= 0;
|
|
else if(rx_wb_writeback_finished & RxEn & RxEn_q)
|
// Switch over whenever we've finished receiving last frame's data
|
// Switch over whenever we've finished receiving last frame's data
|
rx_wbside_fifo_sel <= ~rx_wbside_fifo_sel;
|
rx_wbside_fifo_sel <= ~rx_wbside_fifo_sel;
|
|
|
reg LatchedRxStartFrm;
|
|
reg SyncRxStartFrm;
|
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reg SyncRxStartFrm_q;
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reg SyncRxStartFrm_q2;
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wire RxFifoReset;
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|
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
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if(Reset)
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LatchedRxStartFrm <= 0;
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LatchedRxStartFrm <= 0;
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else
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else
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| Line 2302... |
Line 2365... |
end
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end
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wire rx_startfrm_wb;
|
wire rx_startfrm_wb;
|
assign rx_startfrm_wb = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
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assign rx_startfrm_wb = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
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|
|
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assign RxFifoReset = rx_startfrm_wb;
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assign RxFifoReset = rx_startfrm_wb | rx_discard_packet | overflow_bug_reset;
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wire [31:0] rx_fifo0_data_out;
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wire rx_fifo0_write;
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wire rx_fifo0_read;
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wire rx_fifo0_clear;
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wire rx_fifo0_full;
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wire rx_fifo0_afull;
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wire rx_fifo0_empty;
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wire rx_fifo0_aempty;
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wire [31:0] rx_fifo1_data_out;
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wire rx_fifo1_write;
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wire rx_fifo1_read;
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wire rx_fifo1_clear;
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wire rx_fifo1_full;
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wire rx_fifo1_afull;
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wire rx_fifo1_empty;
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wire rx_fifo1_aempty;
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wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo0_cnt;
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wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo1_cnt;
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// RX FIFO buffer 0 controls
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// RX FIFO buffer 0 controls
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assign rx_fifo0_write = (!rx_ethside_fifo_sel) & WriteRxDataToFifo_wb &
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assign rx_fifo0_write = (!rx_ethside_fifo_sel) & WriteRxDataToFifo_wb &
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~rx_fifo0_full;
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~rx_fifo0_full;
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| Line 2404... |
Line 2445... |
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assign RxBufferFull = rx_wbside_fifo_sel ?
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assign RxBufferFull = rx_wbside_fifo_sel ?
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rx_fifo1_full : rx_fifo0_full;
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rx_fifo1_full : rx_fifo0_full;
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wire write_rx_data_to_memory_wait;
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assign write_rx_data_to_memory_wait = !RxBDOK | RxPointerRead;
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assign write_rx_data_to_memory_wait = !RxBDOK | RxPointerRead;
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wire write_rx_data_to_memory_go;
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`ifdef ETH_RX_BURST_EN
|
`ifdef ETH_RX_BURST_EN
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assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=(`ETH_BURST_LENGTH);
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assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=(`ETH_BURST_LENGTH);
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assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>(`ETH_BURST_LENGTH - 1);
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assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>(`ETH_BURST_LENGTH - 1);
|
// While receiving, don't flog the bus too hard, only write out when
|
// While receiving, don't flog the bus too hard, only write out when
|
| Line 2469... |
Line 2506... |
rx_wb_last_writes <= 1'b0;
|
rx_wb_last_writes <= 1'b0;
|
else if (!rx_wb_last_writes)
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else if (!rx_wb_last_writes)
|
rx_wb_last_writes <= ShiftEndedSync1 & ~ShiftEndedSync2;
|
rx_wb_last_writes <= ShiftEndedSync1 & ~ShiftEndedSync2;
|
else if (rx_wb_writeback_finished & RxEn & RxEn_q)
|
else if (rx_wb_writeback_finished & RxEn & RxEn_q)
|
rx_wb_last_writes <= 0;
|
rx_wb_last_writes <= 0;
|
|
else if (rx_discard_packet | overflow_bug_reset)
|
|
rx_wb_last_writes <= 0;
|
|
|
// Pulse indicating last of RX data has been written out
|
// Pulse indicating last of RX data has been written out
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
if(Reset)
|
if(Reset)
|
rx_wb_writeback_finished <= 0;
|
rx_wb_writeback_finished <= 0;
|
| Line 2502... |
Line 2541... |
// Generation of the end-of-frame signal
|
// Generation of the end-of-frame signal
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxEnableWindow <= 1'b0;
|
RxEnableWindow <= 1'b0;
|
else
|
else if(RxStartFrm)
|
if(RxStartFrm)
|
|
RxEnableWindow <= 1'b1;
|
RxEnableWindow <= 1'b1;
|
else
|
else if(RxEndFrm | RxAbort)
|
if(RxEndFrm | RxAbort)
|
|
RxEnableWindow <= 1'b0;
|
RxEnableWindow <= 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
| Line 2583... |
Line 2620... |
if(LoadRxStatus)
|
if(LoadRxStatus)
|
LatchedRxLength[15:0] <= RxLength[15:0];
|
LatchedRxLength[15:0] <= RxLength[15:0];
|
end
|
end
|
|
|
|
|
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
|
assign RxStatusIn = {ReceivedPauseFrm,
|
|
AddressMiss,
|
|
RxOverrun,
|
|
InvalidSymbol,
|
|
DribbleNibble,
|
|
ReceivedPacketTooBig,
|
|
ShortFrame,
|
|
LatchedCrcError,
|
|
RxLateCollision};
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxStatusInLatched <= 'h0;
|
RxStatusInLatched <= 'h0;
|
| Line 2600... |
Line 2645... |
// Rx overrun
|
// Rx overrun
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxOverrun <= 1'b0;
|
RxOverrun <= 1'b0;
|
else
|
else if(RxStatusWrite | rx_discard_packet | overflow_bug_reset)
|
if(RxStatusWrite)
|
|
RxOverrun <= 1'b0;
|
RxOverrun <= 1'b0;
|
else
|
else if(RxBufferFull & WriteRxDataToFifo_wb)
|
if(RxBufferFull & WriteRxDataToFifo_wb)
|
|
RxOverrun <= 1'b1;
|
RxOverrun <= 1'b1;
|
end
|
end
|
|
|
|
|
|
assign TxError = TxUnderRun | RetryLimit | LateCollLatched |
|
|
CarrierSenseLost;
|
|
|
wire TxError;
|
|
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
|
|
|
|
wire RxError;
|
|
|
|
// ShortFrame (RxStatusInLatched[2]) can not set an error because short
|
// ShortFrame (RxStatusInLatched[2]) can not set an error because short
|
// frames are aborted when signal r_RecSmall is set to 0 in MODER register.
|
// frames are aborted when signal r_RecSmall is set to 0 in MODER register.
|
// AddressMiss is identifying that a frame was received because of the
|
// AddressMiss is identifying that a frame was received because of the
|
// promiscous mode and is not an error
|
// promiscous mode and is not an error
|
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
|
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
|
|
|
|
|
|
|
reg RxStatusWriteLatched;
|
|
reg RxStatusWriteLatched_sync1;
|
|
reg RxStatusWriteLatched_sync2;
|
|
reg RxStatusWriteLatched_syncb1;
|
|
reg RxStatusWriteLatched_syncb2;
|
|
|
|
|
|
// Latching and synchronizing RxStatusWrite signal. This signal is used for
|
// Latching and synchronizing RxStatusWrite signal. This signal is used for
|
// clearing the ReceivedPauseFrm signal
|
// clearing the ReceivedPauseFrm signal
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 2744... |
Line 2778... |
RxBDRead) & rx_startfrm_wb)
|
RxBDRead) & rx_startfrm_wb)
|
rxstartfrm_occurred <= 1;
|
rxstartfrm_occurred <= 1;
|
|
|
|
|
|
|
reg busy_wb;
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
if(Reset)
|
if(Reset)
|
busy_wb <= 0;
|
busy_wb <= 0;
|
else if (busy_wb)
|
else if (busy_wb)
|
busy_wb <= 0;
|
busy_wb <= 0;
|
| Line 2781... |
Line 2814... |
assign dbg_dat0[30:28] = rx_burst_cnt;
|
assign dbg_dat0[30:28] = rx_burst_cnt;
|
assign dbg_dat0[27] = 0;
|
assign dbg_dat0[27] = 0;
|
assign dbg_dat0[26:24] = tx_burst_cnt;
|
assign dbg_dat0[26:24] = tx_burst_cnt;
|
|
|
// Third byte
|
// Third byte
|
assign dbg_dat0[23] = 0;
|
assign dbg_dat0[23] = rx_ethside_fifo_sel;
|
assign dbg_dat0[22] = 0;
|
assign dbg_dat0[22] = rx_wbside_fifo_sel;
|
assign dbg_dat0[21] = rx_burst;
|
assign dbg_dat0[21] = rx_fifo0_empty;
|
assign dbg_dat0[20] = rx_burst_en;
|
assign dbg_dat0[20] = rx_fifo1_empty;
|
assign dbg_dat0[19] = 0;
|
assign dbg_dat0[19] = overflow_bug_reset;
|
assign dbg_dat0[18] = 0;
|
assign dbg_dat0[18] = RxBDOK;
|
assign dbg_dat0[17] = tx_burst;
|
assign dbg_dat0[17] = write_rx_data_to_memory_go;
|
assign dbg_dat0[16] = tx_burst_en;
|
assign dbg_dat0[16] = rx_wb_last_writes;
|
// Second byte - TxBDAddress - or TX BD address pointer
|
// Second byte - TxBDAddress - or TX BD address pointer
|
assign dbg_dat0[15:8] = { 1'b0, TxBDAddress};
|
assign dbg_dat0[15:8] = { BlockingTxBDRead , TxBDAddress};
|
// Bottom byte - FSM controlling vector
|
// Bottom byte - FSM controlling vector
|
assign dbg_dat0[7:0] = {MasterWbTX,MasterWbRX,
|
assign dbg_dat0[7:0] = {MasterWbTX,
|
ReadTxDataFromMemory_2,WriteRxDataToMemory,
|
MasterWbRX,
|
MasterAccessFinished,cyc_cleared,
|
ReadTxDataFromMemory_2,
|
tx_burst,rx_burst};
|
WriteRxDataToMemory,
|
|
MasterAccessFinished,
|
|
cyc_cleared,
|
|
tx_burst,
|
|
rx_burst};
|
|
|
`endif
|
`endif
|
|
|
|
|
|
|
