| Line 63... |
Line 63... |
l.movhi r27, 0
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l.movhi r27, 0
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l.movhi r28, 0
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l.movhi r28, 0
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l.movhi r29, 0
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l.movhi r29, 0
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l.movhi r30, 0
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l.movhi r30, 0
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l.movhi r31, 0
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l.movhi r31, 0
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/* Clear status register, set supervisor mode */
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/* Clear status register, set supervisor mode */
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l.ori r1, r0, SPR_SR_SM
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l.ori r1, r0, SPR_SR_SM
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l.mtspr r0, r1, SPR_SR
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l.mtspr r0, r1, SPR_SR
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/* Clear timer */
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/* Clear timer */
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l.mtspr r0, r0, SPR_TTMR
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l.mtspr r0, r0, SPR_TTMR
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| Line 194... |
Line 195... |
/* ========================================================= [ entry ] === */
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/* ========================================================= [ entry ] === */
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.section .text
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.section .text
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ENTRY(_start)
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ENTRY(_start)
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/* Cache initialisation */
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l.jal _cache_init
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/* Instruction cache enable */
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/* Check if IC present and skip enabling otherwise */
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l.mfspr r24,r0,SPR_UPR
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l.andi r26,r24,SPR_UPR_ICP
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l.sfeq r26,r0
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l.bf .L8
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l.nop
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/* Disable IC */
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l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_ICE
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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/* Establish cache block size
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If BS=0, 16;
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If BS=1, 32;
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r14 contain block size
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*/
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l.mfspr r24,r0,SPR_ICCFGR
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l.andi r26,r24,SPR_ICCFGR_CBS
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l.srli r28,r26,7
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l.ori r30,r0,16
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l.sll r14,r30,r28
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/* Establish number of cache sets
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r16 contains number of cache sets
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r28 contains log(# of cache sets)
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*/
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l.andi r26,r24,SPR_ICCFGR_NCS
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l.srli r28,r26,3
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l.ori r30,r0,1
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l.sll r16,r30,r28
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/* Invalidate IC */
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l.addi r6,r0,0
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l.sll r5,r14,r28
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.L7:
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l.mtspr r0,r6,SPR_ICBIR
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l.sfne r6,r5
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l.bf .L7
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l.add r6,r6,r14
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/* Enable IC */
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l.mfspr r6,r0,SPR_SR
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l.ori r6,r6,SPR_SR_ICE
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l.mtspr r0,r6,SPR_SR
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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.L8:
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/* Data cache enable */
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/* Check if DC present and skip enabling otherwise */
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l.mfspr r24,r0,SPR_UPR
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l.andi r26,r24,SPR_UPR_DCP
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l.sfeq r26,r0
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l.bf .L10
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l.nop
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l.nop
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/* Disable DC */
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l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_DCE
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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/* Establish cache block size
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If BS=0, 16;
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If BS=1, 32;
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r14 contain block size
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*/
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l.mfspr r24,r0,SPR_DCCFGR
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l.andi r26,r24,SPR_DCCFGR_CBS
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l.srli r28,r26,7
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l.ori r30,r0,16
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l.sll r14,r30,r28
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/* Establish number of cache sets
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r16 contains number of cache sets
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r28 contains log(# of cache sets)
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*/
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l.andi r26,r24,SPR_DCCFGR_NCS
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l.srli r28,r26,3
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l.ori r30,r0,1
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l.sll r16,r30,r28
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/* Invalidate DC */
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l.addi r6,r0,0
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l.sll r5,r14,r28
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.L9:
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l.mtspr r0,r6,SPR_DCBIR
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l.sfne r6,r5
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l.bf .L9
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l.add r6,r6,r14
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/* Enable DC */
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l.mfspr r6,r0,SPR_SR
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l.ori r6,r6,SPR_SR_DCE
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l.mtspr r0,r6,SPR_SR
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.L10:
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/* Clear BSS */
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/* Clear BSS */
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LOAD_SYMBOL_2_GPR(r28, _bss_start)
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LOAD_SYMBOL_2_GPR(r5, _bss_start)
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LOAD_SYMBOL_2_GPR(r30, _bss_end)
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LOAD_SYMBOL_2_GPR(r6, _bss_end)
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1:
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1:
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l.sw (0)(r28), r0
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l.sw (0)(r5), r0
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l.sfltu r28, r30
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l.sfltu r5, r6
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l.bf 1b
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l.bf 1b
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l.addi r28, r28, 4
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l.addi r5, r5, 4
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/* Initialise UART in a C function */
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/*l.jal _uart_init
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l.nop*/
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/* Jump to main program entry point (argc = argv = 0) */
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/* Jump to main program entry point (argc = argv = 0) */
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CLEAR_GPR(r3)
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CLEAR_GPR(r3)
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CLEAR_GPR(r4)
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CLEAR_GPR(r4)
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l.jal main
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l.jal main
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