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// ####ECOSGPLCOPYRIGHTEND####
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//#####DESCRIPTIONBEGIN####
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//
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//
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// Author(s): Scott Furman
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// Author(s): Scott Furman
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// Contributors:
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// Contributors:Piotr Skrzypek
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// Date: 2003-02-08
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// Date: 2003-02-08
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// Purpose: Cache control API
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// Purpose: Cache control API
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// Description: The macros defined here provide the HAL APIs for handling
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// Description: The macros defined here provide the HAL APIs for handling
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// cache control operations.
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// cache control operations.
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// Usage:
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// Usage:
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//
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//
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//####DESCRIPTIONEND####
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//####DESCRIPTIONEND####
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//
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//
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//=============================================================================
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//=============================================================================
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//-----------------------------------------------------------------------------
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#ifndef __ASSEMBLER__
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// Cache dimensions.
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// These really should be defined in var_cache.h. If they are not, then provide
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// a set of numbers that are typical of many variants.
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#ifndef HAL_DCACHE_SIZE
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#include <cyg/hal/plf_cache.h>
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#include <cyg/hal/hal_arch.h>
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//-----------------------------------------------------------------------------
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// Data cache
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// Data cache
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#define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
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//
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#define HAL_DCACHE_LINE_SIZE 16 // Bytes in a data cache line
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// If HAL_DCACHE_SIZE is undefined, assume that device does not implement
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#define HAL_DCACHE_WAYS 1 // Associativity of the cache
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// data cache. Provide set of empty macros.
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#ifndef HAL_DCACHE_SIZE
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// Instruction cache
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//Enable the data cache
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#define HAL_ICACHE_SIZE 8192 // Size of cache in bytes
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#define HAL_DCACHE_ENABLE()
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#define HAL_ICACHE_LINE_SIZE 16 // Bytes in a cache line
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#define HAL_ICACHE_WAYS 1 // Associativity of the cache
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#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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//Disable the data cache
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#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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#define HAL_DCACHE_DISABLE()
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#endif
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//Invalidate the entire cache
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#define HAL_DCACHE_INVALIDATE_ALL()
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#ifndef __ASSEMBLER__
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//Synchronize the contents of the cache with memory
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#define HAL_DCACHE_SYNC()
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#include <cyg/hal/hal_arch.h>
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// Query the state of the data cache
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#define HAL_DCACHE_IS_ENABLED(_state_) \
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CYG_MACRO_START \
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(_state_) = 0; \
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CYG_MACRO_END
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//-----------------------------------------------------------------------------
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// If HAL_DCACHE_SIZE is defined, then implement proper macros.
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// Global control of data cache
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#else //#ifndef HAL_DCACHE_SIZE
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// Enable the data cache
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// Enable the data cache
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#define HAL_DCACHE_ENABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) | SPR_SR_DCE)
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#define HAL_DCACHE_ENABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) | SPR_SR_DCE)
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// Disable the data cache
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// Disable the data cache
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#define HAL_DCACHE_DISABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) & ~SPR_SR_DCE)
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#define HAL_DCACHE_DISABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) & ~SPR_SR_DCE)
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// Enable or disable the data cache, depending on argument, which is required
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// Support macro. Enable or disable the data cache, depending on argument,
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// to be 0 or 1.
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// which is required to be 0 or 1.
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#define HAL_SET_DCACHE_ENABLED(enable) \
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#define HAL_SET_DCACHE_ENABLED(enable) \
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MTSPR(SPR_SR, MFSPR(SPR_SR) | (SPR_SR_DCE & -(enable)))
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MTSPR(SPR_SR, MFSPR(SPR_SR) | (SPR_SR_DCE & -(enable)))
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// Invalidate the entire data cache
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// Invalidate the entire data cache
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#define HAL_DCACHE_INVALIDATE_ALL() \
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#define HAL_DCACHE_INVALIDATE_ALL() \
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/* Re-enable cache if it was enabled on entry */ \
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/* Re-enable cache if it was enabled on entry */ \
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HAL_SET_DCACHE_ENABLED(cache_enabled); \
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HAL_SET_DCACHE_ENABLED(cache_enabled); \
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CYG_MACRO_END
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CYG_MACRO_END
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// Synchronize the contents of the cache with memory.
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// Synchronize the contents of the cache with memory.
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// (Unnecessary on OR12K, since cache is write-through.)
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#define HAL_DCACHE_SYNC() HAL_DCACHE_FLUSH(0, HAL_DCACHE_SIZE)
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#define HAL_DCACHE_SYNC() \
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CYG_MACRO_START \
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CYG_MACRO_END
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// Query the state (enabled/disabled) of the data cache
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// Query the state of the data cache
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#define HAL_DCACHE_IS_ENABLED(_state_) \
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#define HAL_DCACHE_IS_ENABLED(_state_) \
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CYG_MACRO_START \
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CYG_MACRO_START \
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(_state_) = (1 - !(MFSPR(SPR_SR) & SPR_SR_DCE)); \
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(_state_) = (1 - !(MFSPR(SPR_SR) & SPR_SR_DCE)); \
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CYG_MACRO_END
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CYG_MACRO_END
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// Load the contents of the given address range into the data cache
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// and then lock the cache so that it stays there.
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// The OpenRISC architecture defines these operations, but no
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// implementation supports them yet.
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//#define HAL_DCACHE_LOCK(_base_, _size_)
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// Undo a previous lock operation
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//#define HAL_DCACHE_UNLOCK(_base_, _size_)
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// Unlock entire cache
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//#define HAL_DCACHE_UNLOCK_ALL()
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//-----------------------------------------------------------------------------
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// Data cache line control
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// Write dirty cache lines to memory and invalidate the cache entries
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// Write dirty cache lines to memory and invalidate the cache entries
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// for the given address range.
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// for the given address range.
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// OR12k has write-through cache, so no flushing of writes to memory
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// are necessary.
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#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
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#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
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HAL_DCACHE_INVALIDATE(_base_, _size_)
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CYG_MACRO_START \
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int addr; \
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int end = _base_ + _size_ - 1; \
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for (addr = end; addr >= _base_; addr -= HAL_DCACHE_LINE_SIZE) { \
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MTSPR(SPR_DCBFR, addr); \
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} \
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CYG_MACRO_END
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// Invalidate cache lines in the given range without writing to memory.
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// Invalidate cache lines in the given range without writing to memory
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#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
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#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
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CYG_MACRO_START \
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CYG_MACRO_START \
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int addr; \
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int addr; \
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int end = _base_ + _size_; \
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int end = _base_ + _size_ - 1; \
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for (addr = end; addr >= _base_; addr -= HAL_DCACHE_LINE_SIZE) { \
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for (addr = end; addr >= _base_; addr -= HAL_DCACHE_LINE_SIZE) { \
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MTSPR(SPR_DCBIR, addr); \
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MTSPR(SPR_DCBIR, addr); \
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} \
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} \
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CYG_MACRO_END
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CYG_MACRO_END
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// Write dirty cache lines to memory for the given address range.
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// Write dirty cache lines to memory for the given address range
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// OR12k has write-through cache, so this is a NOP
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#if defined(HAL_DCACHE_MODE_WRITETHROUGH)
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#define HAL_DCACHE_STORE( _base_ , _size_ )
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#define HAL_DCACHE_STORE( _base_ , _size_ )
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// Preread the given range into the cache with the intention of reading
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#elif defined(HAL_DCACHE_MODE_WRITEBACK)
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// from it later.
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//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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#define HAL_DCACHE_STORE( _base_ , _size_ ) \
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CYG_MACRO_START \
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// Preread the given range into the cache with the intention of writing
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int addr; \
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// to it later.
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int end = _base_ + _size_ - 1; \
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//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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for (addr = end; addr >= _base_; addr -= HAL_DCACHE_LINE_SIZE) { \
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MTSPR(SPR_DCBWR, addr); \
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} \
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CYG_MACRO_END
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#else
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#error Unsupported cache mode
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#endif
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// Allocate and zero the cache lines associated with the given range.
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#endif //#ifndef HAL_DCACHE_SIZE
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//#define HAL_DCACHE_ZERO( _base_ , _size_ )
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Global control of Instruction cache
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// Instruction cache
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//
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// If HAL_ICACHE_SIZE is undefined, assume that device does not implement
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// instruction cache. Provide set of empty macros.
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#ifndef HAL_ICACHE_SIZE
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// Enable the instruction cache
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#define HAL_ICACHE_ENABLE()
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// Disable the instruction cache
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#define HAL_ICACHE_DISABLE()
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// Invalidate the entire cache
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#define HAL_ICACHE_INVALIDATE_ALL()
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// Synchronize the contents of the cache with memory.
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#define HAL_ICACHE_SYNC()
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// Query the state of the instruction cache (does not affect the caching)
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#define HAL_ICACHE_IS_ENABLED(_state_) \
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CYG_MACRO_START \
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(_state_) = 0; \
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CYG_MACRO_END
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#else //#ifndef HAL_ICACHE_SIZE
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// Enable the instruction cache
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// Enable the instruction cache
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#define HAL_ICACHE_ENABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) | SPR_SR_ICE)
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#define HAL_ICACHE_ENABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) | SPR_SR_ICE)
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// Disable the instruction cache
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// Disable the instruction cache
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#define HAL_ICACHE_DISABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) & ~SPR_SR_ICE)
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#define HAL_ICACHE_DISABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) & ~SPR_SR_ICE)
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// Enable or disable the data cache, depending on argument, which must
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// Support macro. Enable or disable the data cache, depending on argument,
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// be 0 or 1.
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// which must be 0 or 1.
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#define HAL_SET_ICACHE_ENABLED(enable) \
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#define HAL_SET_ICACHE_ENABLED(enable) \
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MTSPR(SPR_SR, MFSPR(SPR_SR) | (SPR_SR_ICE & -(enable)))
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MTSPR(SPR_SR, MFSPR(SPR_SR) | (SPR_SR_ICE & -(enable)))
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// Invalidate the entire instruction cache
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// Invalidate the entire instruction cache
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#define HAL_ICACHE_INVALIDATE_ALL() \
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#define HAL_ICACHE_INVALIDATE_ALL() \
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#define HAL_ICACHE_IS_ENABLED(_state_) \
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#define HAL_ICACHE_IS_ENABLED(_state_) \
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CYG_MACRO_START \
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CYG_MACRO_START \
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(_state_) = (1 - !(MFSPR(SPR_SR) & SPR_SR_ICE)); \
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(_state_) = (1 - !(MFSPR(SPR_SR) & SPR_SR_ICE)); \
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CYG_MACRO_END
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CYG_MACRO_END
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#endif //#ifndef HAL_ICACHE_SIZE
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// Load the contents of the given address range into the instruction cache
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// and then lock the cache so that it stays there.
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// The OpenRISC architecture defines these operations, but no
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// implementation supports them yet.
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//#define HAL_ICACHE_LOCK(_base_, _size_)
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// Undo a previous lock operation
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//#define HAL_ICACHE_UNLOCK(_base_, _size_)
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// Unlock entire cache
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//#define HAL_ICACHE_UNLOCK_ALL()
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#endif /* __ASSEMBLER__ */
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#endif /* __ASSEMBLER__ */
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#endif // ifndef CYGONCE_HAL_CACHE_H
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#endif // ifndef CYGONCE_HAL_CACHE_H
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// End of hal_cache.h
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// End of hal_cache.h
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