| Line 400... |
Line 400... |
load32i r4,0x100
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load32i r4,0x100
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load32i r3,rom_vectors
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load32i r3,rom_vectors
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load32i r5,rom_vectors_end
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load32i r5,rom_vectors_end
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1: l.sfeq r3,r5
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1: l.sfeq r3,r5
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l.bf 2f
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l.bf 2f
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l.lwz r6,0(r3)
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l.lwz r6,0(r3) # Note that this might be a branch slot
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l.sw 0(r4),r6
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l.sw 0(r4),r6
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l.addi r3,r3,4
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l.addi r3,r3,4
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#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
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#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
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l.j 1b
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l.j 1b
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l.addi r4,r4,4 # delay slot
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l.addi r4,r4,4 # delay slot
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| Line 418... |
Line 418... |
load32i r3,__rom_data_start
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load32i r3,__rom_data_start
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load32i r4,__ram_data_start
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load32i r4,__ram_data_start
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load32i r5,__ram_data_end
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load32i r5,__ram_data_end
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1: l.sfeq r4,r5
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1: l.sfeq r4,r5
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l.bf 2f
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l.bf 2f
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l.lwz r6,0(r3)
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l.lwz r6,0(r3) # Note that this might be a branch slot
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l.sw 0(r4),r6
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l.sw 0(r4),r6
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l.addi r3,r3,4
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l.addi r3,r3,4
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#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
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#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
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l.j 1b
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l.j 1b
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l.addi r4,r4,4 # delay slot
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l.addi r4,r4,4 # delay slot
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| Line 565... |
Line 565... |
l.or r6,sp,sp # Stash SP for later
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l.or r6,sp,sp # Stash SP for later
|
load32i r7,__interrupt_stack # stack top (highest addr + 1)
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load32i r7,__interrupt_stack # stack top (highest addr + 1)
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load32i r8,__interrupt_stack_base # stack base (lowest addr)
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load32i r8,__interrupt_stack_base # stack base (lowest addr)
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l.sfltu sp,r8 # if (sp < __interrupt_stack_base)
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l.sfltu sp,r8 # if (sp < __interrupt_stack_base)
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l.bf 1f # switch to interrupt stack
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l.bf 1f # switch to interrupt stack
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l.sfltu sp,r7 # if (sp < __interrupt_stack_top)
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l.sfltu sp,r7 # Note that this might be a branch slot
|
|
# if (sp < __interrupt_stack_top)
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l.bf 2f # already on interrupt stack
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l.bf 2f # already on interrupt stack
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#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
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#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.nop # delay slot
|
l.nop # delay slot
|
#endif
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#endif
|
1: l.or sp,r7,r7 # Switch to interrupt stack
|
1: l.or sp,r7,r7 # Switch to interrupt stack
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| Line 647... |
Line 648... |
check_for_external_interrupts:
|
check_for_external_interrupts:
|
l.ori r3,r0,0
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l.ori r3,r0,0
|
2: l.andi r11,r9,1 # Test low bit
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2: l.andi r11,r9,1 # Test low bit
|
l.sfnei r11,0
|
l.sfnei r11,0
|
l.bf 3f
|
l.bf 3f
|
l.srli r9,r9,1 # Shift right 1 bit
|
l.srli r9,r9,1 # Shift right 1 bit, note that this might be a branch slot
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.j 2b
|
l.j 2b
|
l.addi r3,r3,1 # Delay slot
|
l.addi r3,r3,1 # Delay slot
|
#else
|
#else
|
l.addi r3,r3,1
|
l.addi r3,r3,1
|
| Line 793... |
Line 794... |
l.lwz r3, 3 * OR1K_GPRSIZE(sp)
|
l.lwz r3, 3 * OR1K_GPRSIZE(sp)
|
l.lwz sp, 1 * OR1K_GPRSIZE(sp)
|
l.lwz sp, 1 * OR1K_GPRSIZE(sp)
|
|
|
# All done, restore CPU state and continue
|
# All done, restore CPU state and continue
|
l.rfe
|
l.rfe
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
# l.rfe does not have a branch slot
|
l.nop # Delay slot
|
|
#endif
|
|
|
|
|
|
##-----------------------------------------------------------------------------
|
##-----------------------------------------------------------------------------
|
## Execute pending DSRs on the interrupt stack with interrupts enabled.
|
## Execute pending DSRs on the interrupt stack with interrupts enabled.
|
## Note: this can only be called from code running on a thread stack
|
## Note: this can only be called from code running on a thread stack
|
