URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [openrisc/] [arch/] [current/] [src/] [vectors.S] - Diff between revs 843 and 844

Rev 843	Rev 844
Line 565...	Line 565...
`l.or r6,sp,sp # Stash SP for later`	`l.or r6,sp,sp # Stash SP for later`
`load32i r7,__interrupt_stack # stack top (highest addr + 1)`	`load32i r7,__interrupt_stack # stack top (highest addr + 1)`
`load32i r8,__interrupt_stack_base # stack base (lowest addr)`	`load32i r8,__interrupt_stack_base # stack base (lowest addr)`
`l.sfltu sp,r8 # if (sp < __interrupt_stack_base)`	`l.sfltu sp,r8 # if (sp < __interrupt_stack_base)`
`l.bf 1f # switch to interrupt stack`	`l.bf 1f # switch to interrupt stack`
`l.sfltu sp,r7 # Note that this might be a branch slot`	`l.sfltu sp,r7 # if (sp < __interrupt_stack_top) (note this might be a branch slot)`
`# if (sp < __interrupt_stack_top)`
`l.bf 2f # already on interrupt stack`	`l.bf 2f # already on interrupt stack`
`#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED`	`#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED`
`l.nop # delay slot`	`l.nop # delay slot`
`#endif`	`#endif`
`1: l.or sp,r7,r7 # Switch to interrupt stack`	`1: l.or sp,r7,r7 # Switch to interrupt stack`