OpenCores
URL https://opencores.org/ocsvn/or1200gct/or1200gct/trunk

Subversion Repositories or1200gct

[/] [or1200gct/] [trunk/] [or1200_config.v] - Diff between revs 6 and 9

Show entire file | Details | Blame | View Log

Rev 6 Rev 9
Line 1... Line 1...
 
`define OR1200_GENERIC
 
`define OR1200_GENERIC_MULTP2_32X32
 
`define OR1200_RFRAM_GENERIC
 
`define OR1200_REGISTERED_OUTPUTS
 
`define OR1200_WB_CAB
 
`define OR1200_CASE_DEFAULT
 
`define OR1200_IMPL_MEM2REG1
 
`define OR1200_SR_EPH_DEF 1'b1
 
`define OR1200_IMPL_CY
 
`define OR1200_MULT_IMPLEMENTED
 
`define OR1200_PM_READREGS
 
`define OR1200_PM_UNUSED_ZERO
 
`define OR1200_PM_PARTIAL_DECODING
 
`define OR1200_DU_READREGS
 
`define OR1200_DU_UNUSED_ZERO
 
`define OR1200_DU_STATUS_UNIMPLEMENTED
 
`define OR1200_PIC_IMPLEMENTED
 
`define OR1200_PIC_READREGS
 
`define OR1200_PIC_UNUSED_ZERO
 
`define OR1200_PIC_PICMR
 
`define OR1200_PIC_PICSR
 
`define OR1200_PIC_INTS 20
 
`define OR1200_TT_IMPLEMENTED
 
`define OR1200_TT_TTMR
 
`define OR1200_TT_TTSR
 
`define OR1200_TT_READREGS
 
`define OR1200_NO_IC
 
`define OR1200_IC_1W_8KB
 
`define OR1200_ICLS 4
 
`define OR1200_NO_DC
 
`define OR1200_DC_1W_8KB
 
`define OR1200_DCLS 4
 
`define OR1200_SB_ENTRIES 4
 
`define OR1200_SB_LOG 2
 
`define OR1200_NO_IMMU
 
`define OR1200_NO_DMMU
 
`define OR1200_MAC_SPR_WE
 
`define OR1200_CFGR_IMPLEMENTED
 
`define OR1200_SYS_FULL_DECODE
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.