| Line 33... |
Line 33... |
ins1 (a2,v1,a1,v3,v5,a0,e0,e1,e2,e3,e4,e5,in0), // $in0$ is the first input
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ins1 (a2,v1,a1,v3,v5,a0,e0,e1,e2,e3,e4,e5,in0), // $in0$ is the first input
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ins2 (b2,v2,b1,v4,v6,b0,e0,e1,e2,e3,e4,e5,in1); // $in1$ is the second input
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ins2 (b2,v2,b1,v4,v6,b0,e0,e1,e2,e3,e4,e5,in1); // $in1$ is the second input
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f32m_mult
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f32m_mult
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ins3 (clk, mult_reset, in0, in1, o, mult_done); // o == in0 * in1
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ins3 (clk, mult_reset, in0, in1, o, mult_done); // o == in0 * in1
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func6
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func6
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ins4 (clk, mult_done, p);
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ins4 (clk, reset, mult_done, p);
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f32m_add
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f32m_add
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ins5 (a1, a2, v1), // v1 == a1+a2
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ins5 (a1, a2, v1), // v1 == a1+a2
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ins6 (b1, b2, v2), // v2 == b1+b2
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ins6 (b1, b2, v2), // v2 == b1+b2
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ins7 (a0, a2, v3), // v3 == a0+a2
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ins7 (a0, a2, v3), // v3 == a0+a2
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ins8 (b0, b2, v4), // v4 == b0+b2
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ins8 (b0, b2, v4), // v4 == b0+b2
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| Line 57... |
Line 57... |
ins19 (x3, x2, nx0, nx5, d2); // d2 == x3+x2-x0-x5
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ins19 (x3, x2, nx0, nx5, d2); // d2 == x3+x2-x0-x5
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (reset) K <= 7'b1000000;
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if (reset) K <= 7'b1000000;
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else if (p) K <= {1'b0,K[6:1]};
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else if (p | K[0]) K <= {1'b0,K[6:1]};
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (e0) x0 <= o; // x0 == a2*b2
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if (e0) x0 <= o; // x0 == a2*b2
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| Line 116... |
Line 116... |
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always @ (posedge clk)
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always @ (posedge clk)
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c <= {c2,c1,c0};
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c <= {c2,c1,c0};
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endmodule
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endmodule
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// c == a ^ { 3^{3*M} - 1 } in GF(3^{6M})
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module second_part(clk, reset, a, c, done);
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input clk, reset;
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input [`W6:0] a;
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output reg [`W6:0] c;
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output reg done;
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reg [3:0] K;
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wire [`WIDTH:0] d0,d1,d2,d3,d4,d5,
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c0,c1,c2,c3,c4,c5;
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wire [`W3:0] a0,a1,b0,b1,
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v1,v2,v3,v4,v5,v6,v7,v8,nv6;
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wire [1:0] v9,v10;
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wire rst1, rst2, rst3, done1, done2, done3;
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assign {d5,d4,d3,d2,d1,d0} = a;
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assign {a1,a0} = {d5,d3,d1,d4,d2,d0}; // change basis
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assign {b1,b0} = {{v8[`W3:2],v10}, {v7[`W3:2],v9}};
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assign {c5,c3,c1,c4,c2,c0} = {b1,b0}; // change basis back
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assign rst1 = reset;
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f33m_mult2
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ins1 (clk, rst1,
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a0, a0, v1, // v1 == a0^2
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a1, a1, v2, // v2 == a1^2
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done1);
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f33m_add
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ins2 (v1, v2, v3), // v3 == v1+v2 == a0^2+a1^2
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ins3 (a0, a1, v5); // v5 == a0+a1
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f33m_inv
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ins4 (clk, rst2, v3, v4, done2); // v4 == v3^{-1} == (a0^2+a1^2)^{-1}
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f33m_neg
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ins5 (v6, nv6); // nv6 == -v6 == -(a0+a1)^2
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f33m_mult3 // ****** $v8$ depends on $v6$ ******
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ins6 (clk, rst3,
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v5, v5, v6, // v6 == v5^2 == (a0+a1)^2
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v2, v4, v7, // v7 == v2*v4 == (a1^2)*{(a0^2+a1^2)^{-1}}
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nv6, v4, v8, // v8 == -v6*v4
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done3);
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f3_add1
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ins7 (v7[1:0], v9), // v9 == v7[1:0]+1
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ins8 (v8[1:0], v10); // v10 == v8[1:0]+1
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func6
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ins9 (clk, reset, done1, rst2),
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ins10 (clk, reset, done2, rst3);
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always @ (posedge clk)
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if (reset) K <= 4'b1000;
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else if ((K[3]&rst2)|(K[2]&rst3)|(K[1]&done3)|K[0])
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K <= K >> 1;
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always @ (posedge clk)
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if (reset) done <= 0;
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else if (K[0])
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begin
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done <= 1; c <= {c5,c4,c3,c2,c1,c0};
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end
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endmodule
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