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[/] [pairing/] [trunk/] [rtl/] [f3m.v] - Diff between revs 7 and 8

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Line 1... Line 1...
`include "inc.v"
`include "inc.v"
`define MOST 2*`M+1:2*`M
`define MOST 2*`M+1:2*`M
 
 
// out = (v1 & l1) | (v2 & l2)
 
module f3m_mux2(v1, l1, v2, l2, out);
 
    input [`WIDTH:0] v1, v2;
 
    input l1, l2;
 
    output [`WIDTH:0] out;
 
    genvar i;
 
    generate
 
        for(i=0;i<=`WIDTH;i=i+1)
 
          begin : label
 
            assign out[i] = (v1[i] & l1) | (v2[i] & l2);
 
          end
 
    endgenerate
 
endmodule
 
 
 
// out = (v1 & l1) | (v2 & l2) | (v3 & l3)
// out = (v1 & l1) | (v2 & l2) | (v3 & l3)
module f3m_mux3(v1, l1, v2, l2, v3, l3, out);
module f3m_mux3(v1, l1, v2, l2, v3, l3, out);
    input [`WIDTH:0] v1, v2, v3;
    input [`WIDTH:0] v1, v2, v3;
    input l1, l2, l3;
    input l1, l2, l3;
    output [`WIDTH:0] out;
    output [`WIDTH:0] out;
Line 112... Line 98...
    output reg [`WIDTH : 0] C;
    output reg [`WIDTH : 0] C;
    output reg done;
    output reg done;
    reg [`WIDTH : 0] x, y, z;
    reg [`WIDTH : 0] x, y, z;
    wire [`WIDTH : 0] z1, z2, z4;
    wire [`WIDTH : 0] z1, z2, z4;
    wire [`WIDTH+2 : 0] z3;
    wire [`WIDTH+2 : 0] z3;
    reg [`M+1 : 0] i;
    reg [`M : 0] i;
    wire [`M+1 : 0] i1;
 
    wire done1;
    wire done1;
    wire [1:0] dummy;
    wire [1:0] dummy;
 
 
    func4
    func4
        ins1 ({2'b0,x}, y[1:0], {dummy,z1}); // z1 == A * B[0]
        ins1 ({2'b0,x}, y[1:0], {dummy,z1}); // z1 == A * B[0]
    f3m_add
    f3m_add
        ins2 (z1, z, z2); // z2 == z1 + z == A*B[0] + z
        ins2 (z1, z, z2); // z2 == z1 + z == A*B[0] + z
    assign z4 = {2'd0, y[`WIDTH:2]}; // z4 == y >> 2
    assign z4 = {2'd0, y[`WIDTH:2]}; // z4 == y >> 2
    func3
    func3
        ins3 ({2'd0,x}, z3); // z3 == X*x mod p(x)
        ins3 ({2'd0,x}, z3); // z3 == X*x mod p(x)
    assign i1 = {1'b0, i[`M+1:1]}; // i1 == i >> 1
    assign done1 = i[0];
    assign done1 = (i1[1:0] == 2'b01);
 
 
 
    always @ (posedge clk)
    always @ (posedge clk)
        if (done1)
        if (done1)
          begin
 
            C <= z;
            C <= z;
          end
 
 
 
    always @ (posedge clk)
    always @ (posedge clk)
        if (reset)
        if (reset)
            done <= 0;
            done <= 0;
        else if (done1)
        else if (done1)
Line 143... Line 125...
 
 
    always @ (posedge clk)
    always @ (posedge clk)
      begin
      begin
        if (reset)
        if (reset)
          begin
          begin
            x <= A; y <= B; z <= 0; i <= ~0;
            x <= A; y <= B; z <= 0; i <= {1'b1,{`M{1'b0}}};
          end
          end
        else
        else
          begin
          begin
            x <= z3[`WIDTH:0]; y <= z4; z <= z2; i <= i1;
            x <= z3[`WIDTH:0]; y <= z4; z <= z2; i <= i >> 1;
          end
          end
      end
      end
endmodule
endmodule
 
 
// c0 == a0*b0; c1 == a1*b1; c2 == a2*b2; all in GF(3^M)
// c0 == a0*b0; c1 == a1*b1; c2 == a2*b2; all in GF(3^M)
Line 176... Line 158...
        ins9 (a0, e1, a1, e2, a2, e3, in1),
        ins9 (a0, e1, a1, e2, a2, e3, in1),
        ins10 (b0, e1, b1, e2, b2, e3, in2);
        ins10 (b0, e1, b1, e2, b2, e3, in2);
    f3m_mult
    f3m_mult
        ins11 (clk, mult_reset, in1, in2, o, mult_done); // o == in1 * in2 in GF(3^m)
        ins11 (clk, mult_reset, in1, in2, o, mult_done); // o == in1 * in2 in GF(3^m)
    func6
    func6
        ins12 (clk, mult_done, delay3);
        ins12 (clk, reset, mult_done, delay3);
 
 
    always @ (posedge clk)
    always @ (posedge clk)
      begin
      begin
        if (e1) c0 <= o;
        if (e1) c0 <= o;
        if (e2) c1 <= o;
        if (e2) c1 <= o;
        if (e3) c2 <= o;
        if (e3) c2 <= o;
      end
      end
 
 
    always @ (posedge clk)
    always @ (posedge clk)
        if (reset) K <= 4'b1000;
        if (reset) K <= 4'b1000;
        else if (delay3) K <= {1'b0,K[3:1]};
        else if (delay3 | K[0]) K <= {1'b0,K[3:1]};
 
 
    always @ (posedge clk)
    always @ (posedge clk)
      begin
      begin
        if (rst) mult_reset <= 1;
        if (rst) mult_reset <= 1;
        else if (mult_done) mult_reset <= 1;
        else if (mult_done) mult_reset <= 1;
Line 490... Line 472...
        input clk;
        input clk;
        input reset;
        input reset;
        output reg [`WIDTH:0] C;
        output reg [`WIDTH:0] C;
    output reg done;
    output reg done;
 
 
        reg [`WIDTH+2:0] S, R, U, V, d, i;
        reg [`WIDTH+2:0] S, R, U, V, d;
 
        reg [2*`M:0] i;
        wire [1:0] q;
        wire [1:0] q;
        wire [`WIDTH+2:0] S1, S2,
        wire [`WIDTH+2:0] S1, S2,
                          R1,
                          R1,
                          U1, U2, U3,
                          U1, U2, U3,
                          V1, V2,
                          V1, V2,
                          d1, d2,
                          d1, d2;
                      i1;
 
        wire don;
        wire don;
 
 
        assign d1 = {d[`WIDTH+1:0], 1'b1}; // d1 == d+1
        assign d1 = {d[`WIDTH+1:0], 1'b1}; // d1 == d+1
        assign d2 = {1'b0, d[`WIDTH+2:1]}; // d2 == d-1
        assign d2 = {1'b0, d[`WIDTH+2:1]}; // d2 == d-1
    assign i1 = {1'b0, i[`WIDTH+2:1]}; // i1 == i-1
        assign don = i[0];
        assign don = (i[2:1] == 2'b01);
 
 
 
        always @ (posedge clk)
 
        if (reset)
 
            done <= 0;
 
            else if (don)
 
          begin
 
                done <= 1; C <= U2[`WIDTH:0];
 
          end
 
 
 
        f3_mult
        f3_mult
            q1(S[`MOST], R[`MOST], q); // q = s_m / r_m
            q1(S[`MOST], R[`MOST], q); // q = s_m / r_m
        func1
        func1
            ins1(S, R, q, S1), // S1 = S - q*R
            ins1(S, R, q, S1), // S1 = S - q*R
Line 531... Line 504...
    func5
    func5
        ins8(U, U3); // U3 = (U/x) mod p
        ins8(U, U3); // U3 = (U/x) mod p
 
 
    always @ (posedge clk)
    always @ (posedge clk)
        if (reset)
        if (reset)
            i <= ~0;
            done <= 0;
 
            else if (don)
 
          begin
 
                done <= 1; C <= U2[`WIDTH:0];
 
          end
 
 
 
    always @ (posedge clk)
 
        if (reset)
 
            i <= {1'b1, {(2*`M){1'b0}}};
        else
        else
            i <= i1;
            i <= i >> 1;
 
 
    always @ (posedge clk)
    always @ (posedge clk)
        if (reset)
        if (reset)
          begin
          begin
            S<=`PX; R<=A; U<=1; V<=0; d<=0;
            S<=`PX; R<=A; U<=1; V<=0; d<=0;

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