| Line 3... |
Line 3... |
-- Title : ctrl_ram_cmd
|
-- Title : ctrl_ram_cmd
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-- Author : Dmitry Smekhov
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-- Author : Dmitry Smekhov
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-- Company : Instrumental Systems
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-- Company : Instrumental Systems
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-- E-mail : dsmv@insys.ru
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-- E-mail : dsmv@insys.ru
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--
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--
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-- Version : 1.4
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-- Version : 1.5
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Description : Узел управления памятью
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-- Description : Узел управления памятью
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--
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--
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
|
|
-- Version 1.5 07.03.2016
|
|
-- Исправлено формирование ram_adrb при is_dsp48=0
|
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--
|
|
-------------------------------------------------------------------------------
|
|
--
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-- Version 1.4 09.04.2012
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-- Version 1.4 09.04.2012
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-- Исправлено формирование
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-- Исправлено формирование
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-- ch0_next_block, ch1_next_block
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-- ch0_next_block, ch1_next_block
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--
|
--
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
| Line 505... |
Line 510... |
|
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gen_ndsp48: if( is_dsp48=0 ) generate
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gen_ndsp48: if( is_dsp48=0 ) generate
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|
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port_p( 47 downto 9 ) <= (others=>'0');
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port_p( 47 downto 9 ) <= (others=>'0');
|
|
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pr_dsp: process( clk ) begin
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pr_dsp: process( aclk ) begin
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if( rising_edge( clk ) ) then
|
if( rising_edge( aclk ) ) then
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if( cnt_rstp='1' ) then
|
if( cnt_rstp='1' ) then
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port_p( 8 downto 0 ) <= (others=>'0' ) after 1 ns;
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port_p( 8 downto 0 ) <= (others=>'0' ) after 1 ns;
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elsif( carry='1' ) then
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elsif( carry='1' ) then
|
port_p( 8 downto 0 ) <= port_p( 8 downto 0 ) + 1 after 1 ns;
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port_p( 8 downto 0 ) <= port_p( 8 downto 0 ) + 1 after 1 ns;
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end if;
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end if;
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