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-- PART OF THIS FILE AT ALL TIMES.
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-- PART OF THIS FILE AT ALL TIMES.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Project : Series-7 Integrated Block for PCI Express
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-- Project : Series-7 Integrated Block for PCI Express
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-- File : cl_a7pcie_x4_axi_basic_rx_null_gen.vhd
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-- File : cl_a7pcie_x4_axi_basic_rx_null_gen.vhd
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-- Version : 1.10
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-- Version : 1.11
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--
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--
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-- Description:
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-- Description:
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-- TRN to AXI RX null generator. Generates null packets for use in discontinue situations.
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-- TRN to AXI RX null generator. Generates null packets for use in discontinue situations.
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--
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--
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-- Notes:
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-- Notes:
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constant INTERFACE_WIDTH_DWORDS : integer := if_wdt_dw(C_DATA_WIDTH);
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constant INTERFACE_WIDTH_DWORDS : integer := if_wdt_dw(C_DATA_WIDTH);
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constant IDLE : std_logic := '0';
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constant IDLE : std_logic := '0';
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constant IN_PACKET : std_logic := '1';
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constant IN_PACKET : std_logic := '1';
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-- Signals for tracking a packet on the AXI interface
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-- Signals for tracking a packet on the AXI interface
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SIGNAL reg_pkt_len_counter : STD_LOGIC_VECTOR(11 DOWNTO 0);
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SIGNAL reg_pkt_len_counter : STD_LOGIC_VECTOR(11 DOWNTO 0):= (others => '0');
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SIGNAL pkt_len_counter : STD_LOGIC_VECTOR(11 DOWNTO 0);
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SIGNAL pkt_len_counter : STD_LOGIC_VECTOR(11 DOWNTO 0):= (others => '0');
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SIGNAL pkt_len_counter_dec : STD_LOGIC_VECTOR(11 DOWNTO 0);
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SIGNAL pkt_len_counter_dec : STD_LOGIC_VECTOR(11 DOWNTO 0):= (others => '0');
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SIGNAL pkt_done : STD_LOGIC;
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SIGNAL pkt_done : STD_LOGIC:= '0';
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SIGNAL new_pkt_len : STD_LOGIC_VECTOR(11 DOWNTO 0);
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SIGNAL new_pkt_len : STD_LOGIC_VECTOR(11 DOWNTO 0):= (others => '0');
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SIGNAL payload_len : STD_LOGIC_VECTOR(9 DOWNTO 0);
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SIGNAL payload_len : STD_LOGIC_VECTOR(9 DOWNTO 0):= (others => '0');
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SIGNAL payload_len_tmp : STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0');
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SIGNAL payload_len_tmp : STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0');
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SIGNAL packet_fmt : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL packet_fmt : STD_LOGIC_VECTOR(1 DOWNTO 0):= (others => '0');
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SIGNAL packet_td : STD_LOGIC;
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SIGNAL packet_td : STD_LOGIC:= '0';
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SIGNAL packet_overhead : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL packet_overhead : STD_LOGIC_VECTOR(3 DOWNTO 0):= (others => '0');
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-- X-HDL generated signals`
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-- X-HDL generated signals`
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SIGNAL xhdl2 : STD_LOGIC_VECTOR(2 DOWNTO 0);
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SIGNAL xhdl2 : STD_LOGIC_VECTOR(2 DOWNTO 0):= (others => '0');
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SIGNAL reg_is_eof : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL reg_is_eof : STD_LOGIC_VECTOR(4 DOWNTO 0):= (others => '0');
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SIGNAL xhdl5 : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL xhdl5 : STD_LOGIC_VECTOR(1 DOWNTO 0):= (others => '0');
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SIGNAL xhdl7 : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL xhdl7 : STD_LOGIC_VECTOR(1 DOWNTO 0):= (others => '0');
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--State machine variables and states
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--State machine variables and states
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SIGNAL next_state : STD_LOGIC;
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SIGNAL next_state : STD_LOGIC:= '0';
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SIGNAL cur_state : STD_LOGIC;
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SIGNAL cur_state : STD_LOGIC:= '0';
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-- Declare intermediate signals for referenced outputs
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-- Declare intermediate signals for referenced outputs
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SIGNAL null_rx_tlast_xhdl0 : STD_LOGIC;
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SIGNAL null_rx_tlast_xhdl0 : STD_LOGIC:= '0';
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-- Misc.
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-- Misc.
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SIGNAL eof_tkeep : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0);
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SIGNAL eof_tkeep : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0):= (others => '0');
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SIGNAL straddle_sof : STD_LOGIC;
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SIGNAL straddle_sof : STD_LOGIC:= '0';
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SIGNAL eof : STD_LOGIC;
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SIGNAL eof : STD_LOGIC:= '0';
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BEGIN
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BEGIN
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-- Create signals to detect sof and eof situations. These signals vary depending
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-- Create signals to detect sof and eof situations. These signals vary depending
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-- on the data width.
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-- on the data width.
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