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-- PART OF THIS FILE AT ALL TIMES.
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-- PART OF THIS FILE AT ALL TIMES.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Project : Series-7 Integrated Block for PCI Express
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-- Project : Series-7 Integrated Block for PCI Express
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-- File : cl_a7pcie_x4_gt_rx_valid_filter_7x.vhd
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-- File : cl_a7pcie_x4_gt_rx_valid_filter_7x.vhd
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-- Version : 1.10
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-- Version : 1.11
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---- Description: GTX module for 7-series Integrated PCIe Block
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---- Description: GTX module for 7-series Integrated PCIe Block
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----
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----
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----
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----
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----
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----
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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constant EIOS_COM : std_logic_vector(7 downto 0) := X"BC";
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constant EIOS_COM : std_logic_vector(7 downto 0) := X"BC";
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constant EIOS_IDL : std_logic_vector(7 downto 0) := X"7C";
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constant EIOS_IDL : std_logic_vector(7 downto 0) := X"7C";
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constant FTSOS_COM : std_logic_vector(7 downto 0) := X"BC";
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constant FTSOS_COM : std_logic_vector(7 downto 0) := X"BC";
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constant FTSOS_FTS : std_logic_vector(7 downto 0) := X"3C";
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constant FTSOS_FTS : std_logic_vector(7 downto 0) := X"3C";
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signal reg_state_eios_det : std_logic_vector(4 downto 0);
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signal reg_state_eios_det : std_logic_vector(4 downto 0):= (others => '0');
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signal state_eios_det : std_logic_vector(4 downto 0);
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signal state_eios_det : std_logic_vector(4 downto 0):= (others => '0');
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signal reg_eios_detected : std_logic;
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signal reg_eios_detected : std_logic:= '0';
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signal eios_detected : std_logic;
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signal eios_detected : std_logic:= '0';
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signal reg_symbol_after_eios : std_logic;
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signal reg_symbol_after_eios : std_logic:= '0';
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signal symbol_after_eios : std_logic;
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signal symbol_after_eios : std_logic:= '0';
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constant USER_RXVLD_IDL : std_logic_vector(3 downto 0) := "0001";
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constant USER_RXVLD_IDL : std_logic_vector(3 downto 0) := "0001";
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constant USER_RXVLD_EI : std_logic_vector(3 downto 0) := "0010";
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constant USER_RXVLD_EI : std_logic_vector(3 downto 0) := "0010";
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constant USER_RXVLD_EI_DB0 : std_logic_vector(3 downto 0) := "0100";
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constant USER_RXVLD_EI_DB0 : std_logic_vector(3 downto 0) := "0100";
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constant USER_RXVLD_EI_DB1 : std_logic_vector(3 downto 0) := "1000";
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constant USER_RXVLD_EI_DB1 : std_logic_vector(3 downto 0) := "1000";
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signal gt_rxcharisk_q : std_logic_vector( 1 downto 0);
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signal gt_rxcharisk_q : std_logic_vector( 1 downto 0):= (others => '0');
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signal gt_rxdata_q : std_logic_vector(15 downto 0);
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signal gt_rxdata_q : std_logic_vector(15 downto 0):= (others => '0');
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signal gt_rxvalid_q : std_logic;
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signal gt_rxvalid_q : std_logic:= '0';
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signal gt_rxelecidle_q : std_logic;
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signal gt_rxelecidle_q : std_logic:= '0';
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signal gt_rx_status_q : std_logic_vector( 2 downto 0);
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signal gt_rx_status_q : std_logic_vector( 2 downto 0):= (others => '0');
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signal gt_rx_phy_status_q : std_logic;
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signal gt_rx_phy_status_q : std_logic:= '0';
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signal gt_rx_is_skp0_q : std_logic;
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signal gt_rx_is_skp0_q : std_logic:= '0';
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signal gt_rx_is_skp1_q : std_logic;
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signal gt_rx_is_skp1_q : std_logic:= '0';
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begin
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begin
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-- EIOS detector
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-- EIOS detector
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