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-- PART OF THIS FILE AT ALL TIMES.
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-- PART OF THIS FILE AT ALL TIMES.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Project : Series-7 Integrated Block for PCI Express
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-- Project : Series-7 Integrated Block for PCI Express
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-- File : cl_a7pcie_x4_gt_top.vhd
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-- File : cl_a7pcie_x4_gt_top.vhd
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-- Version : 1.10
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-- Version : 1.11
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---- Description: GTX module for 7-series Integrated PCIe Block
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---- Description: GTX module for 7-series Integrated PCIe Block
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----
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----
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----
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----
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----
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----
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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| Line 503... |
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constant EI_DELAY : integer := get_ei_delay(PL_FAST_TRAIN);
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constant EI_DELAY : integer := get_ei_delay(PL_FAST_TRAIN);
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constant PCIE_OOBCLK_MODE_ENABLE : integer := get_oobclk_mode(PL_FAST_TRAIN);
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constant PCIE_OOBCLK_MODE_ENABLE : integer := get_oobclk_mode(PL_FAST_TRAIN);
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constant signal_z : std_logic_vector((18*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0) := (others => '0');
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constant signal_z : std_logic_vector((18*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0) := (others => '0');
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signal gt_rx_phy_status_wire : std_logic_vector(7 downto 0);
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signal gt_rx_phy_status_wire : std_logic_vector(7 downto 0):= (others => '0');
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signal gt_rxchanisaligned_wire : std_logic_vector(7 downto 0);
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signal gt_rxchanisaligned_wire : std_logic_vector(7 downto 0):= (others => '0');
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signal gt_rx_data_k_wire : std_logic_vector(31 downto 0);
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signal gt_rx_data_k_wire : std_logic_vector(31 downto 0):= (others => '0');
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signal gt_rx_data_wire : std_logic_vector(255 downto 0);
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signal gt_rx_data_wire : std_logic_vector(255 downto 0):= (others => '0');
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signal gt_rx_elec_idle_wire : std_logic_vector(7 downto 0);
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signal gt_rx_elec_idle_wire : std_logic_vector(7 downto 0):= (others => '0');
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signal gt_rx_status_wire : std_logic_vector(23 downto 0);
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signal gt_rx_status_wire : std_logic_vector(23 downto 0):= (others => '0');
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signal gt_rx_valid_wire : std_logic_vector(7 downto 0);
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signal gt_rx_valid_wire : std_logic_vector(7 downto 0):= (others => '0');
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signal gt_rx_polarity : std_logic_vector(7 downto 0);
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signal gt_rx_polarity : std_logic_vector(7 downto 0):= (others => '0');
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signal gt_power_down : std_logic_vector(15 downto 0);
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signal gt_power_down : std_logic_vector(15 downto 0):= (others => '0');
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signal gt_tx_char_disp_mode : std_logic_vector(7 downto 0);
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signal gt_tx_char_disp_mode : std_logic_vector(7 downto 0):= (others => '0');
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signal gt_tx_data_k : std_logic_vector(31 downto 0);
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signal gt_tx_data_k : std_logic_vector(31 downto 0):= (others => '0');
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signal gt_tx_data : std_logic_vector(255 downto 0);
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signal gt_tx_data : std_logic_vector(255 downto 0):= (others => '0');
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signal gt_tx_detect_rx_loopback : std_logic;
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signal gt_tx_detect_rx_loopback : std_logic:= '0';
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signal gt_tx_elec_idle : std_logic_vector(7 downto 0);
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signal gt_tx_elec_idle : std_logic_vector(7 downto 0):= (others => '0');
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signal gt_rx_elec_idle_reset : std_logic_vector(7 downto 0);
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signal gt_rx_elec_idle_reset : std_logic_vector(7 downto 0):= (others => '0');
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signal plllkdet : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
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signal plllkdet : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0):= (others => '0');
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signal phystatus_rst : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
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signal phystatus_rst : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0):= (others => '0');
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signal clock_locked : std_logic;
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signal clock_locked : std_logic:= '0';
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signal pipe_rate_concat : std_logic_vector(1 downto 0);
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signal pipe_rate_concat : std_logic_vector(1 downto 0):= (others => '0');
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signal pipe_tx_deemph_concat : std_logic_vector((1*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
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signal pipe_tx_deemph_concat : std_logic_vector((1*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0):= (others => '0');
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signal all_phystatus_rst : std_logic;
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signal all_phystatus_rst : std_logic:= '0';
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signal gt_rx_phy_status_wire_filter : std_logic_vector( 7 downto 0);
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signal gt_rx_phy_status_wire_filter : std_logic_vector( 7 downto 0):= (others => '0');
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signal gt_rx_data_k_wire_filter : std_logic_vector( 31 downto 0);
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signal gt_rx_data_k_wire_filter : std_logic_vector( 31 downto 0):= (others => '0');
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signal gt_rx_data_wire_filter : std_logic_vector(255 downto 0);
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signal gt_rx_data_wire_filter : std_logic_vector(255 downto 0):= (others => '0');
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signal gt_rx_elec_idle_wire_filter : std_logic_vector( 7 downto 0);
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signal gt_rx_elec_idle_wire_filter : std_logic_vector( 7 downto 0):= (others => '0');
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signal gt_rx_status_wire_filter : std_logic_vector( 23 downto 0);
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signal gt_rx_status_wire_filter : std_logic_vector( 23 downto 0):= (others => '0');
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signal gt_rx_valid_wire_filter : std_logic_vector( 7 downto 0);
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signal gt_rx_valid_wire_filter : std_logic_vector( 7 downto 0):= (others => '0');
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signal pl_ltssm_state_q : std_logic_vector( 5 downto 0);
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signal pl_ltssm_state_q : std_logic_vector( 5 downto 0):= (others => '0');
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signal plm_in_l0 : std_logic;
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signal plm_in_l0 : std_logic:= '0';
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signal plm_in_rl : std_logic;
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signal plm_in_rl : std_logic:= '0';
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signal plm_in_dt : std_logic;
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signal plm_in_dt : std_logic:= '0';
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signal plm_in_rs : std_logic;
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signal plm_in_rs : std_logic:= '0';
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signal pipe_clk_int : std_logic;
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signal pipe_clk_int : std_logic:= '0';
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signal phy_rdy_n_int : std_logic;
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signal phy_rdy_n_int : std_logic:= '0';
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signal reg_clock_locked : std_logic;
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signal reg_clock_locked : std_logic:= '0';
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begin
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begin
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-- Register pl_ltssm_state
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-- Register pl_ltssm_state
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