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URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source_artix7/] [cl_a7pcie_x4_pcie_7x.vhd] - Diff between revs 48 and 49

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Rev 48 Rev 49
Line 47... Line 47... 
-- PART OF THIS FILE AT ALL TIMES.
 
-- PART OF THIS FILE AT ALL TIMES.
 
--
 
--
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- Project    : Series-7 Integrated Block for PCI Express
 
-- Project    : Series-7 Integrated Block for PCI Express
 
-- File       : cl_a7pcie_x4_pcie_7x.vhd
 
-- File       : cl_a7pcie_x4_pcie_7x.vhd
 
-- Version    : 1.10
 
-- Version    : 1.11
 
--
 
--
 
-- Description: Solution wrapper for Virtex7 Hard Block for PCI Express
 
-- Description: Solution wrapper for Virtex7 Hard Block for PCI Express
 
--
 
--
 
--
 
--
 
--
 
--
Line 538... Line 538... 
  drp_clk                                        : in std_logic;
 
  drp_clk                                        : in std_logic;
 
  drp_en                                         : in std_logic;
 
  drp_en                                         : in std_logic;
 
  drp_we                                         : in std_logic;
 
  drp_we                                         : in std_logic;
 
  drp_addr                                       : in std_logic_vector(8 downto 0);
 
  drp_addr                                       : in std_logic_vector(8 downto 0);
 
  drp_di                                         : in std_logic_vector(15 downto 0);
 
  drp_di                                         : in std_logic_vector(15 downto 0);
 
  drp_rdy                                        : out std_logic;
 
  drp_rdy                                        : out std_logic := '0' ;
 
  drp_do                                         : out std_logic_vector(15 downto 0);
 
  drp_do                                         : out std_logic_vector(15 downto 0):= (others => '0');
 
  dbg_mode                                       : in std_logic_vector(1 downto 0);
 
  dbg_mode                                       : in std_logic_vector(1 downto 0);
 
  dbg_sub_mode                                   : in std_logic;
 
  dbg_sub_mode                                   : in std_logic;
 
  pl_dbg_mode                                    : in std_logic_vector( 2 downto 0);
 
  pl_dbg_mode                                    : in std_logic_vector( 2 downto 0);
 
 
 
 
 
  trn_clk                                        : out std_logic;
 
  trn_clk                                        : out std_logic;

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