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// PART OF THIS FILE AT ALL TIMES.
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// PART OF THIS FILE AT ALL TIMES.
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_pipe_reset.v
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// File : cl_a7pcie_x4_pipe_reset.v
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// Version : 1.9
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// Version : 1.10
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Filename : pipe_reset.v
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// Filename : pipe_reset.v
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// Description : PIPE Reset Module for 7 Series Transceiver
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// Description : PIPE Reset Module for 7 Series Transceiver
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// Version : 20.0
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// Version : 20.2
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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input [PCIE_LANE-1:0] RST_TXSYNC_DONE,
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input [PCIE_LANE-1:0] RST_TXSYNC_DONE,
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//---------- Output ------------------------------------
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//---------- Output ------------------------------------
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output RST_CPLLRESET,
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output RST_CPLLRESET,
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output RST_CPLLPD,
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output RST_CPLLPD,
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output RST_DRP_START,
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output reg RST_DRP_START,
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output RST_DRP_X16X20_MODE,
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output reg RST_DRP_X16X20_MODE,
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output RST_DRP_X16,
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output reg RST_DRP_X16,
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output RST_RXUSRCLK_RESET,
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output RST_RXUSRCLK_RESET,
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output RST_DCLK_RESET,
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output RST_DCLK_RESET,
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output RST_GTRESET,
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output RST_GTRESET,
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output RST_USERRDY,
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output RST_USERRDY,
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output RST_TXSYNC_START,
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output RST_TXSYNC_START,
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output [ 4:0] RST_FSM
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output [ 4:0] RST_FSM
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);
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);
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//---------- Input Register ----------------------------
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//---------- Input Register ----------------------------
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reg [PCIE_LANE-1:0] drp_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg1;
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reg [PCIE_LANE-1:0] rxpmaresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg1;
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reg [PCIE_LANE-1:0] cplllock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg1;
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reg qpll_idle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qpll_idle_reg1;
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reg [PCIE_LANE-1:0] rate_idle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg1;
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reg [PCIE_LANE-1:0] rxcdrlock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg1;
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reg mmcm_lock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
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reg [PCIE_LANE-1:0] resetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg1;
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reg [PCIE_LANE-1:0] phystatus_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg1;
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reg [PCIE_LANE-1:0] txsync_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg1;
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reg [PCIE_LANE-1:0] drp_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg2;
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reg [PCIE_LANE-1:0] rxpmaresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg2;
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reg [PCIE_LANE-1:0] cplllock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg2;
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reg qpll_idle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qpll_idle_reg2;
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reg [PCIE_LANE-1:0] rate_idle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg2;
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reg [PCIE_LANE-1:0] rxcdrlock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg2;
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reg mmcm_lock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
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reg [PCIE_LANE-1:0] resetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg2;
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reg [PCIE_LANE-1:0] phystatus_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg2;
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reg [PCIE_LANE-1:0] txsync_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg2;
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//---------- Internal Signal ---------------------------
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//---------- Internal Signal ---------------------------
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reg [ 5:0] cfg_wait_cnt = 6'd0;
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reg [ 5:0] cfg_wait_cnt = 6'd0;
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//---------- Output Register ---------------------------
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//---------- Output Register ---------------------------
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reg cpllreset = 1'd0;
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reg cpllreset = 1'd0;
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reg cpllpd = 1'd0;
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reg cpllpd = 1'd0;
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reg rxusrclk_rst_reg1 = 1'd0;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxusrclk_rst_reg1 = 1'd0;
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reg rxusrclk_rst_reg2 = 1'd0;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxusrclk_rst_reg2 = 1'd0;
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reg dclk_rst_reg1 = 1'd0;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg dclk_rst_reg1 = 1'd0;
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reg dclk_rst_reg2 = 1'd0;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg dclk_rst_reg2 = 1'd0;
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reg gtreset = 1'd0;
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reg gtreset = 1'd0;
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reg userrdy = 1'd0;
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reg userrdy = 1'd0;
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reg [ 4:0] fsm = 2;
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reg [4:0] fsm = 5'h2;
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//---------- FSM ---------------------------------------
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//---------- FSM ---------------------------------------
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localparam FSM_IDLE = 0;
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localparam FSM_IDLE = 5'h0;
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localparam FSM_CFG_WAIT = 1;
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localparam FSM_CFG_WAIT = 5'h1;
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localparam FSM_CPLLRESET = 2;
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localparam FSM_CPLLRESET = 5'h2;
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localparam FSM_DRP_X16_START = 3;
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localparam FSM_DRP_X16_START = 5'h3;
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localparam FSM_DRP_X16_DONE = 4;
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localparam FSM_DRP_X16_DONE = 5'h4;
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localparam FSM_CPLLLOCK = 5;
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localparam FSM_CPLLLOCK = 5'h5;
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localparam FSM_DRP = 6;
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localparam FSM_DRP = 5'h6;
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localparam FSM_GTRESET = 7;
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localparam FSM_GTRESET = 5'h7;
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localparam FSM_RXPMARESETDONE_1 = 8;
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localparam FSM_RXPMARESETDONE_1 = 5'h8;
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localparam FSM_RXPMARESETDONE_2 = 9;
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localparam FSM_RXPMARESETDONE_2 = 5'h9;
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localparam FSM_DRP_X20_START = 10;
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localparam FSM_DRP_X20_START = 5'hA;
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localparam FSM_DRP_X20_DONE = 11;
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localparam FSM_DRP_X20_DONE = 5'hB;
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localparam FSM_MMCM_LOCK = 12;
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localparam FSM_MMCM_LOCK = 5'hC;
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localparam FSM_RESETDONE = 13;
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localparam FSM_RESETDONE = 5'hD;
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localparam FSM_CPLL_PD = 14;
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localparam FSM_CPLL_PD = 5'hE;
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localparam FSM_TXSYNC_START = 15;
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localparam FSM_TXSYNC_START = 5'hF;
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localparam FSM_TXSYNC_DONE = 16;
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localparam FSM_TXSYNC_DONE = 5'h10;
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//---------- Input FF ----------------------------------------------------------
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//---------- Input FF ----------------------------------------------------------
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always @ (posedge RST_CLK)
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always @ (posedge RST_CLK)
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begin
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begin
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if (fsm == FSM_CFG_WAIT)
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if (fsm == FSM_CFG_WAIT)
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begin
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begin
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dclk_rst_reg1 <= 1'd1;
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dclk_rst_reg1 <= 1'd1;
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dclk_rst_reg2 <= 1'd1;
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dclk_rst_reg2 <= dclk_rst_reg1;
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end
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end
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else
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else
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begin
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begin
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dclk_rst_reg1 <= 1'd0;
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dclk_rst_reg1 <= 1'd0;
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dclk_rst_reg2 <= dclk_rst_reg1;
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dclk_rst_reg2 <= dclk_rst_reg1;
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assign RST_CPLLRESET = cpllreset;
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assign RST_CPLLRESET = cpllreset;
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assign RST_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd);
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assign RST_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd);
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assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2;
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assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2;
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assign RST_DCLK_RESET = dclk_rst_reg2;
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assign RST_DCLK_RESET = dclk_rst_reg2;
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assign RST_GTRESET = gtreset;
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assign RST_GTRESET = gtreset;
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assign RST_DRP_START = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
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assign RST_DRP_X16X20_MODE = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) || (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE);
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assign RST_DRP_X16 = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
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assign RST_USERRDY = userrdy;
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assign RST_USERRDY = userrdy;
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assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START);
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assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START);
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assign RST_IDLE = (fsm == FSM_IDLE);
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assign RST_IDLE = (fsm == FSM_IDLE);
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assign RST_FSM = fsm;
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assign RST_FSM = fsm;
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//--------------------------------------------------------------------------------------------------
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// Register Output
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//--------------------------------------------------------------------------------------------------
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always @ (posedge RST_CLK)
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begin
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if (!RST_RST_N)
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begin
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RST_DRP_START <= 1'd0;
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RST_DRP_X16X20_MODE <= 1'd0;
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RST_DRP_X16 <= 1'd0;
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end
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else
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begin
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RST_DRP_START <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
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RST_DRP_X16X20_MODE <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) || (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE);
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RST_DRP_X16 <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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