Subversion Repositories pcie_ds_dma

[file:.\src\pcie_src\components\coregen\ctrl_fifo512x64st_v0.ngc]

Enabled=1

[file:.\src\pcie_src\components\coregen\ctrl_fifo512x64st_v0.xco]

Enabled=1

[file:.\src\pcie_src\components\coregen\ctrl_fifo64x34fw.ngc]

Enabled=1

[file:.\src\pcie_src\components\coregen\ctrl_fifo64x34fw.xco]

Enabled=1

[file:.\src\pcie_src\components\coregen\ctrl_fifo64x37st.ngc]

Enabled=1

[file:.\src\pcie_src\components\coregen\ctrl_fifo64x37st.xco]

Enabled=1

[file:.\src\pcie_src\components\coregen\ctrl_fifo64x67fw.ngc]

Enabled=1

[file:.\src\pcie_src\components\coregen\ctrl_fifo64x67fw.xco]

Enabled=1

[file:.\src\pcie_src\components\coregen\ctrl_fifo64x70st.ngc]

Enabled=1

[file:.\src\pcie_src\components\coregen\ctrl_fifo64x70st.xco]

Enabled=1

[file:.\src\pcie_src\components\coregen\read.me]

Enabled=1

[file:.\src\pcie_src\components\pcie_core\pcie_core64_m2.vhd]

Enabled=0

[file:.\src\pcie_src\components\pcie_core\pcie_core64_m5.vhd]

Enabled=0

[file:.\src\pcie_src\pcie_core64_m1\source\bram_common.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\cfg_wr_enable.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\cmm_decoder.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cnt_en.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cnt_nfl_en.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cor.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cpl.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\cmm_errman_ftl.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\cmm_errman_nfl.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\cmm_errman_ram4x26.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\cmm_errman_ram8x26.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\cmm_intr.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\ctrl_pcie_x8.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\ctrl_pcie_x8.xco]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\extend_clk.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_arb.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_err.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_mgmt.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_pwr.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_if.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_arb.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_credit.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_oqbqfifo.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_tx.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_tx_arb.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_plus_ll_rx.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_plus_ll_tx.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_clocking.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_ep.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_gtx_wrapper.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_gt_wrapper.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_gt_wrapper_top.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_mim_wrapper.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_reset_logic.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_soft_int.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\pcie_top.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\prod_fixes.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\sync_fifo.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk_bar.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk_mal.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk_pwr_mgmt.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\tx_sync_gtp.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\tx_sync_gtx.v]

Enabled=1

[file:.\src\pcie_src\pcie_core64_m1\source\use_newinterrupt.v]

Enabled=1

[file:.\src\top\ambpex5_sx50t_wishbone.vhd]

Enabled=1

[file:.\src\top\ambpex5_sx50t_wishbone_sopc_wb.vhd]

Enabled=1

[file:.\src\wishbone\coregen\ctrl_fifo1024x64_st_v1.ngc]

Enabled=1

[file:.\src\wishbone\coregen\ctrl_fifo1024x64_st_v1.xco]

Enabled=1

[file:.\src\wishbone\cross\read.me]

Enabled=1

[file:.\src\wishbone\doc\en\block_test_check_en.htm]

Enabled=1

[file:.\src\wishbone\doc\en\block_test_generate_en.htm]

Enabled=1

[file:.\src\wishbone\doc\en\style.css]

Enabled=1

[file:.\src\wishbone\doc\en\wishbone_test_en.htm]

Enabled=1

[file:.\src\wishbone\doc\ru\block_test_check.htm]

Enabled=1

[file:.\src\wishbone\doc\ru\block_test_generate.htm]

Enabled=1

[file:.\src\wishbone\doc\ru\style.css]

Enabled=1

[file:.\src\wishbone\doc\ru\wishbonbe_test.htm]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\SciTE.session]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\delete.bat]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\ds_dma_pb_if.v]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\start.bat]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\tb.v]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\wave.do]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\wb_simple_ram_slave_if.v]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\wb_slave_if.v]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do\delete.do]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do\setup_sim.do]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_test_check\SciTE.session]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_test_check\sim\delete.bat]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_test_check\sim\ds_dma_test_check_burst_master_if.v]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_test_check\sim\ds_dma_test_check_burst_master_if.vPreview]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_test_check\sim\start.bat]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_test_check\sim\tb.v]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_test_check\sim\wave.do]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_test_check\sim\zz_do\delete.do]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_test_check\sim\zz_do\setup_sim.do]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_test_gen\SciTE.session]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_test_gen\sim\delete.bat]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_test_gen\sim\ds_dma_test_gen_burst_master_if.v]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_test_gen\sim\start.bat]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_test_gen\sim\tb.v]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_test_gen\sim\wave.do]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_test_gen\sim\zz_do\delete.do]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_test_gen\sim\zz_do\setup_sim.do]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_wb_cross\SciTE.session]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\delete.bat]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\start.bat]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\tb.v]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\wave.do]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_intf.sv]

Enabled=1

VerilogLanguage=7

[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_master.sv]

Enabled=1

VerilogLanguage=7

[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_ram_slave.v]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\delete.do]

Enabled=1

[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\setup_sim.do]

Enabled=1

[file:.\src\testbench\stend_ambpex5_wishbone.vhd]

Enabled=1

[file:.\src\testbench\ahdl\log_example\console_test_adm_read_8kb.log]

Enabled=1

[file:.\src\testbench\ahdl\log_example\console_test_dsc_incorrect.log]

Enabled=1

[file:.\src\testbench\ahdl\log_example\console_test_read_4kB.log]

Enabled=1

[file:.\src\testbench\ahdl\log_example\file_id_0.log]

Enabled=1

[file:.\src\testbench\ahdl\log_example\file_id_1.log]

Enabled=1

[file:.\src\testbench\ahdl\log_example\file_id_2.log]

Enabled=1

[file:.\src\testbench\ahdl\log_example\global_tc_summary.log]

Enabled=1

[file:.\src\testbench\log\file_id_3.log]

Enabled=1

[file:.\src\testbench\modelsim\delete.bat]

Enabled=1

[file:.\src\testbench\modelsim\start.bat]

Enabled=1

[file:.\src\testbench\modelsim\wave.do]

Enabled=1

[file:.\src\testbench\modelsim\required_tests\SciTE.session]

Enabled=1

[file:.\src\testbench\modelsim\required_tests\test0\block_check_wb_burst_slave_0.v]

Enabled=1

[file:.\src\testbench\modelsim\required_tests\test0\delete.bat]

Enabled=1

[file:.\src\testbench\modelsim\required_tests\test0\read.me]

Enabled=1

[file:.\src\testbench\modelsim\required_tests\test0\start.bat]

Enabled=1

[file:.\src\testbench\modelsim\required_tests\test0\wave.do]

Enabled=1

[file:.\src\testbench\modelsim\required_tests\test0\zz_do\delete.do]

Enabled=1

[file:.\src\testbench\modelsim\required_tests\test0\zz_do\setup_sim.do]

Enabled=1

[file:.\src\testbench\modelsim\zz_do\delete.do]

Enabled=1

[file:.\src\testbench\modelsim\zz_do\setup_sim.do]

Enabled=1

[file:.\synthesis\ambpex5_sx50t_wishbone.vhd]

LIB=ambpex5_sx50t_wishbone_post_synthesis

Enabled=1

SIM.FUNC.INCLUDED=0

SIM.POST.INCLUDED=1

SIM.POST.AUTO=1

SIM.POST.INDEX=0

[file:.\src\adm\adm2_pkg.vhd]

Enabled=1

[file:.\src\adm\cl_ambpex5\rtl\ctrl_adsp_v2_decode_cmd_adr_cs.vhd]

Enabled=1

[file:.\src\adm\cl_ambpex5\rtl\ctrl_adsp_v2_decode_data_cs.vhd]

Enabled=1

[file:.\src\adm\cl_ambpex5\rtl\ctrl_adsp_v2_decode_data_in_cs.vhd]

Enabled=1

[file:.\src\adm\cl_ambpex5\rtl\ctrl_adsp_v2_decode_data_we.vhd]

Enabled=1

[file:.\src\adm\cl_ambpex5\rtl\ctrl_adsp_v2_decode_ram_cs.vhd]

Enabled=1

[file:.\src\adm\cl_ambpex5\rtl\ctrl_blink.vhd]

Enabled=1

[file:.\src\adm\cl_ambpex5\rtl\pb_adm_ctrl_m2.vhd]

Enabled=1

[file:.\src\adm\cl_ambpex5\top\cl_ambpex5_m5.vhd]

Enabled=1

[file:.\src\adm\cl_ml605\rtl\ctrl_adsp_v2_decode_cmd_adr_cs.vhd]

Enabled=1

[file:.\src\adm\cl_ml605\rtl\ctrl_adsp_v2_decode_data_cs.vhd]

Enabled=1

[file:.\src\adm\cl_ml605\rtl\ctrl_adsp_v2_decode_data_in_cs.vhd]

Enabled=1

[file:.\src\adm\cl_ml605\rtl\ctrl_adsp_v2_decode_data_we.vhd]

Enabled=1

[file:.\src\adm\cl_ml605\rtl\ctrl_adsp_v2_decode_ram_cs.vhd]

Enabled=1

[file:.\src\adm\cl_ml605\rtl\ctrl_blink.vhd]

Enabled=1

[file:.\src\adm\cl_ml605\rtl\pb_adm_ctrl_m2.vhd]

Enabled=1

[file:.\src\adm\cl_ml605\top\cl_ml605.vhd]

Enabled=1

[file:.\src\adm\cl_sp605\rtl\ctrl_adsp_v2_decode_cmd_adr_cs.vhd]

Enabled=1

[file:.\src\adm\cl_sp605\rtl\ctrl_adsp_v2_decode_data_cs.vhd]

Enabled=1

[file:.\src\adm\cl_sp605\rtl\ctrl_adsp_v2_decode_data_in_cs.vhd]

Enabled=1

[file:.\src\adm\cl_sp605\rtl\ctrl_adsp_v2_decode_data_we.vhd]

Enabled=1

[file:.\src\adm\cl_sp605\rtl\ctrl_adsp_v2_decode_ram_cs.vhd]

Enabled=1

[file:.\src\adm\cl_sp605\rtl\ctrl_blink.vhd]

Enabled=1

[file:.\src\adm\cl_sp605\rtl\pb_adm_ctrl_m2.vhd]

Enabled=1

[file:.\src\adm\cl_sp605\top\cl_sp605.vhd]

Enabled=1

[file:.\src\adm\coregen\ctrl_fifo1024x65_v5.edn]

Enabled=1

[file:.\src\adm\coregen\ctrl_fifo1024x65_v5.vhd]

Enabled=1

[file:.\src\adm\coregen\ctrl_fifo1024x65_v5_fifo_generator_v3_2_xst_1.ngc]

Enabled=1

[file:.\src\adm\coregen\ctrl_multiplier_v1_0.ngc]

Enabled=1

[file:.\src\adm\coregen\ctrl_multiplier_v1_0.vhd]

Enabled=1

[file:.\src\adm\coregen\ctrl_mux16x16.edn]

Enabled=1

[file:.\src\adm\coregen\ctrl_mux16x16.vhd]

Enabled=1

[file:.\src\adm\coregen\ctrl_mux16x64.edn]

Enabled=1

[file:.\src\adm\coregen\ctrl_mux16x64.vhd]

Enabled=1

[file:.\src\adm\coregen\ctrl_mux8x16r.edn]

Enabled=1

[file:.\src\adm\coregen\ctrl_mux8x16r.vhd]

Enabled=1

[file:.\src\adm\coregen\ctrl_mux8x48.edn]

Enabled=1

[file:.\src\adm\coregen\ctrl_mux8x48.vhd]

Enabled=1

[file:.\src\adm\core_s3_empty\ctrl_buft16.vhd]

Enabled=1

[file:.\src\adm\core_s3_empty\ctrl_buft32.vhd]

Enabled=1

[file:.\src\adm\core_s3_empty\ctrl_buft64.vhd]

Enabled=1

[file:.\src\adm\dio64\trd_admdio64_in_v6.vhd]

Enabled=1

[file:.\src\adm\dio64\trd_admdio64_out_v4.vhd]

Enabled=1

[file:.\src\adm\main\cl_chn_v3.vhd]

Enabled=1

[file:.\src\adm\main\cl_chn_v4.vhd]

Enabled=1

[file:.\src\adm\main\cl_test0_v4.vhd]

Enabled=1

[file:.\src\adm\main\cl_test_check.vhd]

Enabled=1

[file:.\src\adm\main\cl_test_generate.vhd]

Enabled=1

[file:.\src\adm\main\ctrl_thdac.vhd]

Enabled=1

[file:.\src\adm\main\trd_main_v8.vhd]

Enabled=1

[file:.\src\adm\main\trd_pio_std_v4.vhd]

Enabled=1

[file:.\src\adm\rtl\cl_fifo1024x65_v5.vhd]

Enabled=1

[file:.\src\adm\rtl\cl_fifo_control_v2.vhd]

Enabled=1

[file:.\src\adm\rtl\ctrl_start_v2.vhd]

Enabled=1

[file:.\src\adm\trd_test_ctrl\ctrl_freq.vhd]

Enabled=1

[file:.\src\adm\trd_test_ctrl\trd_test_ctrl_m1.vhd]

Enabled=1

[file:.\src\testbench\stend_ambpex5_core.vhd]

Enabled=1

[file:.\src\testbench\stend_ambpex5_core_m2.vhd]

Enabled=1

[file:.\src\testbench\modelsim\zz_do\files_coregen_vhdl.f]

Enabled=1

[file:.\src\testbench\modelsim\zz_do\files_design_verilog.f]

Enabled=1

[file:.\src\testbench\modelsim\zz_do\files_design_vhdl.f]

Enabled=1

[file:.\src\testbench\modelsim\zz_do\files_verification_vhdl.f]

Enabled=1

[file:.\src\top\ambpex5_v20_sx50t_core.ucf]

Enabled=1

[file:.\src\top\ambpex5_v20_sx50t_core.vhd]

Enabled=1

[file:.\src\testbench\stend_sp605_core_m2.vhd]

Enabled=1

[file:.\src\testbench\rx.awf]

Enabled=1

[file:.\src\testbench\tx.awf]

Enabled=1

[file:.\src\testbench\disp.awf]

Enabled=1

[file:.\src\testbench\descriptor.awf]

Enabled=1

[file:.\src\top\sp605_lx45t_core.ucf]

Enabled=1

[file:.\src\top\sp605_lx45t_core.vhd]

Enabled=1

[file:.\src\log\test.log]

Enabled=1

[file:.\synthesis\sp605_lx45t_core.vhd]

LIB=sp605_lx45t_core_post_synthesis

Enabled=1

SIM.FUNC.INCLUDED=0

SIM.POST.INCLUDED=1

SIM.POST.AUTO=1

SIM.POST.INDEX=0

[file:.\src\DESIGN_STATUS\2013_07_17_00_56\ComputerInformation.txt]

Enabled=1

[file:.\src\DESIGN_STATUS\2013_07_17_00_56\DesignInformation.txt]

Enabled=1

[file:.\src\DESIGN_STATUS\2013_07_17_00_56\DesignFiles.txt]

Enabled=1

[file:.\src\DESIGN_STATUS\2013_07_17_00_56\LibrariesList.txt]

Enabled=1

[file:.\src\DESIGN_STATUS\2013_07_17_00_56\synthesis_synthesis.dfml]

Enabled=1

[file:.\src\DESIGN_STATUS\2013_07_17_00_56\implement_ver1_rev1_implementation.dfml]

Enabled=1

[file:.\src\testbench\log\console_test_read_reg.log]

Enabled=1

[file:.\src\DESIGN_STATUS\2013_08_02_00_11\ComputerInformation.txt]

Enabled=1

[file:.\src\DESIGN_STATUS\2013_08_02_00_11\DesignInformation.txt]

Enabled=1

[file:.\src\DESIGN_STATUS\2013_08_02_00_11\DesignFiles.txt]

Enabled=1

[file:.\src\DESIGN_STATUS\2013_08_02_00_11\LibrariesList.txt]

Enabled=1

[file:.\src\DESIGN_STATUS\2013_08_02_00_11\synthesis_synthesis.dfml]

Enabled=1

[file:.\src\DESIGN_STATUS\2013_08_02_00_11\implement_ver1_rev1_implementation.dfml]

Enabled=1