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Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [projects/] [sp605_lx45t_wishbone/] [sp605_lx45t_wishbone.adf] - Diff between revs 51 and 53

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Rev 51 Rev 53
Line 41... Line 41... 
HESPrepare=0
 
HESPrepare=0
 
EnableXtrace=0
 
EnableXtrace=0
 
SplitNetVectors=0
 
SplitNetVectors=0
 
StackMemorySize=32
 
StackMemorySize=32
 
RetvalMemorySize=32
 
RetvalMemorySize=32
 
VsimAdditionalOptions=-relax
 
VsimAdditionalOptions=-relax -g test_id=2
 
ReportAssertionsActivations=0
 
ReportAssertionsActivations=0
 
TrackAssertionFailures=1
 
TrackAssertionFailures=1
 
ReportAssertionsFailures=1
 
ReportAssertionsFailures=1
 
AssertionFailureLimit=0
 
AssertionFailureLimit=0
 
AssertionFailureAction=Continue
 
AssertionFailureAction=Continue
Line 73... Line 73... 
TIMING_SIMULATION_STATUS=
 
TIMING_SIMULATION_STATUS=
 
FUNC_LIB=sp605_lx45t_wishbone
 
FUNC_LIB=sp605_lx45t_wishbone
 
POST_LIB=sp605_lx45t_wishbone_post_synthesis
 
POST_LIB=sp605_lx45t_wishbone_post_synthesis
 
RUN_MODE_IMPL=0
 
RUN_MODE_IMPL=0
 
LAST_IMPL_STATUS=warnings
 
LAST_IMPL_STATUS=warnings
 
 
 
resolution=Auto
 
 
 
 
 
[LocalVerilogSets]
 
[LocalVerilogSets]
 
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EnableSLP=1
 
EnableDebug=1
 
EnableDebug=1
 
VerilogLanguage=4
 
VerilogLanguage=4
Line 135... Line 136... 
impl_opt(use_partitions_in_flow)=0
 
impl_opt(use_partitions_in_flow)=0
 
impl_opt(partitions_file)=synthesis\xpartition.pxml
 
impl_opt(partitions_file)=synthesis\xpartition.pxml
 
 
 
 
 
[HierarchyViewer]
 
[HierarchyViewer]
 
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SortInfo=u
 
HierarchyInformation=stend_sp605_wishbone|stend_sp605_wishbone|0
 
HierarchyInformation=pcie_core64_m6|pcie_core64_m6|0 stend_sp605_wishbone|stend_sp605_wishbone|0
 
ShowHide=ShowTopLevel
 
ShowHide=ShowTopLevel
 
Selected=
 
Selected=
 
 
 
 
 
[DefineMacro]
 
[DefineMacro]
 
Global=
 
Global=
Line 491... Line 492... 
 
 
 
 
[Groups]
 
[Groups]
 
pcie_src=1
 
pcie_src=1
 
pcie_src\components=1
 
pcie_src\components=1
 
pcie_src\components\block_main=1
 
pcie_src\components\block_main=1
 
pcie_src\components\coregen=1
 
 
 
pcie_src\components\pcie_core=1
 
pcie_src\components\pcie_core=1
 
pcie_src\components\rtl=1
 
pcie_src\components\rtl=1
 
pcie_src\pcie_core64_m1=1
 
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pcie_src\pcie_core64_m1\pcie_ctrl=1
 
pcie_src\pcie_core64_m1\pcie_fifo_ext=1
 
pcie_src\pcie_core64_m1\pcie_fifo_ext=1
Line 519... Line 519... 
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wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do=1
 
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wishbone\testbecnh\dev_test_check=1
 
wishbone\testbecnh\dev_test_check=1
 
wishbone\testbecnh\dev_test_check\sim=1
 
wishbone\testbecnh\dev_test_check\sim=1
Line 532... Line 532... 
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wishbone\testbecnh\dev_test_gen\sim\zz_do=1
 
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wishbone\testbecnh\dev_wb_cross\sim\zz_do=1
 
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post-synthesis=1
 
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DESIGN_STATUS\2013_08_02_00_11=1
 
DESIGN_STATUS\2013_08_02_00_11=1
 
 
 
wishbone\doc\en=1
 
 
 
wishbone\doc\ru=1
 
 
 
pcie_src\components\coregen_s6=1
 
 
 
 
 
[Files]
 
[Files]
 
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pcie_src\components\coregen/ctrl_fifo64x34fw.vhd=-1
 
 
 
pcie_src\components\coregen/ctrl_fifo64x34fw.xco=-1
 
 
 
pcie_src\components\coregen/ctrl_fifo64x37st.ngc=-1
 
 
 
pcie_src\components\coregen/ctrl_fifo64x37st.vhd=-1
 
 
 
pcie_src\components\coregen/ctrl_fifo64x37st.xco=-1
 
 
 
pcie_src\components\coregen/ctrl_fifo64x67fw.ngc=-1
 
 
 
pcie_src\components\coregen/ctrl_fifo64x67fw.vhd=-1
 
 
 
pcie_src\components\coregen/ctrl_fifo64x67fw.xco=-1
 
 
 
pcie_src\components\coregen/ctrl_fifo64x70st.ngc=-1
 
 
 
pcie_src\components\coregen/ctrl_fifo64x70st.vhd=-1
 
 
 
pcie_src\components\coregen/ctrl_fifo64x70st.xco=-1
 
 
 
pcie_src\components\coregen/ctrl_fifo512x64st_v0.ngc=-1
 
 
 
pcie_src\components\coregen/ctrl_fifo512x64st_v0.vhd=-1
 
 
 
pcie_src\components\coregen/ctrl_fifo512x64st_v0.xco=-1
 
 
 
pcie_src\components\coregen/read.me=-1
 
 
 
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pcie_src\components\pcie_core/pcie_core64_wishbone.vhd=-1
 
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pcie_src\components\rtl/host_pkg.vhd=-1
 
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pcie_src\components\rtl/ctrl_ram16_v1.vhd=-1
 
pcie_src\components\rtl/core64_pb_wishbone.vhd=-1
 
pcie_src\components\rtl/core64_pb_wishbone.vhd=-1
 
pcie_src\components\rtl/core64_pb_wishbone_ctrl.v=-1
 
pcie_src\components\rtl/core64_pb_wishbone_ctrl.v=-1
 
 
 
pcie_src\components\coregen_s6/ctrl_fifo512x64st_v0.ngc=-1
 
 
 
pcie_src\components\coregen_s6/ctrl_fifo512x64st_v0.vhd=-1
 
 
 
pcie_src\components\coregen_s6/ctrl_fifo512x64st_v0.xco=-1
 
 
 
pcie_src\components\coregen_s6/ctrl_fifo64x34fw.ngc=-1
 
 
 
pcie_src\components\coregen_s6/ctrl_fifo64x34fw.vhd=-1
 
 
 
pcie_src\components\coregen_s6/ctrl_fifo64x34fw.xco=-1
 
 
 
pcie_src\components\coregen_s6/ctrl_fifo64x37st.ngc=-1
 
 
 
pcie_src\components\coregen_s6/ctrl_fifo64x37st.vhd=-1
 
 
 
pcie_src\components\coregen_s6/ctrl_fifo64x37st.xco=-1
 
pcie_src\pcie_core64_m1\pcie_ctrl/core64_type_pkg.vhd=-1
 
pcie_src\pcie_core64_m1\pcie_ctrl/core64_type_pkg.vhd=-1
 
pcie_src\pcie_core64_m1\pcie_ctrl/core64_interrupt.vhd=-1
 
pcie_src\pcie_core64_m1\pcie_ctrl/core64_interrupt.vhd=-1
 
pcie_src\pcie_core64_m1\pcie_ctrl/core64_pb_disp.vhd=-1
 
pcie_src\pcie_core64_m1\pcie_ctrl/core64_pb_disp.vhd=-1
 
pcie_src\pcie_core64_m1\pcie_ctrl/core64_reg_access.vhd=-1
 
pcie_src\pcie_core64_m1\pcie_ctrl/core64_reg_access.vhd=-1
 
pcie_src\pcie_core64_m1\pcie_ctrl/core64_rx_engine.vhd=-1
 
pcie_src\pcie_core64_m1\pcie_ctrl/core64_rx_engine.vhd=-1
Line 732... Line 728... 
wishbone\cross/wb_conmax_pri_enc.v=-1
 
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wishbone\cross/wb_conmax_rf.v=-1
 
wishbone\cross/wb_conmax_rf.v=-1
 
wishbone\cross/wb_conmax_slave_if.v=-1
 
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wishbone\cross/wb_conmax_top.v=-1
 
wishbone\cross/wb_conmax_top.v=-1
 
wishbone\cross/wb_conmax_top_pkg.vhd=-1
 
wishbone\cross/wb_conmax_top_pkg.vhd=-1
 
wishbone\doc/block_test_generate.htm=-1
 
wishbone\doc\en/block_test_check_en.htm=-1
 
wishbone\doc/style.css=-1
 
wishbone\doc\en/block_test_generate_en.htm=-1
 
wishbone\doc/block_test_check.htm=-1
 
wishbone\doc\en/style.css=-1
 
wishbone\doc/wishbonbe_test.htm=-1
 
wishbone\doc\en/wishbone_test_en.htm=-1
 
 
 
wishbone\doc\ru/block_test_check.htm=-1
 
 
 
wishbone\doc\ru/block_test_generate.htm=-1
 
 
 
wishbone\doc\ru/style.css=-1
 
 
 
wishbone\doc\ru/wishbonbe_test.htm=-1
 
wishbone\coregen/ctrl_fifo1024x64_st_v1.ngc=-1
 
wishbone\coregen/ctrl_fifo1024x64_st_v1.ngc=-1
 
wishbone\coregen/ctrl_fifo1024x64_st_v1.vhd=-1
 
wishbone\coregen/ctrl_fifo1024x64_st_v1.vhd=-1
 
wishbone\coregen/ctrl_fifo1024x64_st_v1.xco=-1
 
wishbone\coregen/ctrl_fifo1024x64_st_v1.xco=-1
 
wishbone\testbecnh\dev_pb_wishbone_ctrl/SciTE.session=-1
 
wishbone\testbecnh\dev_pb_wishbone_ctrl/SciTE.session=-1
 
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/delete.bat=-1
 
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/delete.bat=-1
Line 792... Line 792... 
DESIGN_STATUS\2013_08_02_00_11/synthesis_synthesis.dfml=-1
 
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DESIGN_STATUS\2013_08_02_00_11/implement_ver1_rev1_implementation.dfml=-1
 
DESIGN_STATUS\2013_08_02_00_11/implement_ver1_rev1_implementation.dfml=-1
 
 
 
 
 
[Files.Data]
 
[Files.Data]
 
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Line 985... Line 978... 
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Line 1043... Line 1040... 
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