| Line 14... |
Line 14... |
#include "pexmodule.h"
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#include "pexmodule.h"
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#include "hardware.h"
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#include "hardware.h"
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#include "ambpexregs.h"
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#include "ambpexregs.h"
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#include "memory.h"
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#include "memory.h"
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int g_isAdm=0;
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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int set_device_name(struct pex_device *brd, u16 dev_id, int index)
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int set_device_name(struct pex_device *brd, u16 dev_id, int index)
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{
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{
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if(!brd)
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if(!brd)
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return -1;
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return -1;
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switch(dev_id) {
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switch(dev_id) {
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case AMBPEX5_DEVID: snprintf(brd->m_name, 128, "%s%d", "AMBPEX5", index); break;
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case AMBPEX5_DEVID: snprintf(brd->m_name, 128, "%s%d", "AMBPEX5", index); break;
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case AMBPEX8_DEVID: snprintf(brd->m_name, 128, "%s%d", "AMBPEX8", index); break;
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case ADP201X1AMB_DEVID: snprintf(brd->m_name, 128, "%s%d", "ADP201X1AMB", index); break;
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case ADP201X1DSP_DEVID: snprintf(brd->m_name, 128, "%s%d", "ADP201X1DSP", index); break;
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case AMBPEXARM_DEVID: snprintf(brd->m_name, 128, "%s%d", "D2XT005", index); break;
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case AMBFMC106P_DEVID: snprintf(brd->m_name, 128, "%s%d", "AMBFMC106P", index); break;
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case AMBFMC114V_DEVID: snprintf(brd->m_name, 128, "%s%d", "AMBFMC114V", index); break;
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case AMBKU_SSCOS_DEVID: snprintf(brd->m_name, 128, "%s%d", "AMBKU_SSCOS", index); break;
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default:
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default:
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snprintf(brd->m_name, sizeof(brd->m_name), "%s%d", "Unknown", index); break;
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snprintf(brd->m_name, sizeof(brd->m_name), "%s%d", "Unknown", index); break;
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}
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}
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return 0;
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return 0;
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| Line 81... |
Line 77... |
deviceID = ReadOperationWordReg(brd, PEMAINadr_DEVICE_ID);
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deviceID = ReadOperationWordReg(brd, PEMAINadr_DEVICE_ID);
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deviceRev = ReadOperationWordReg(brd, PEMAINadr_DEVICE_REV);
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deviceRev = ReadOperationWordReg(brd, PEMAINadr_DEVICE_REV);
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dbg_msg(dbg_trace, "%s(): DeviceID = 0x%X, DeviceRev = 0x%X.\n", __FUNCTION__, deviceID, deviceRev);
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dbg_msg(dbg_trace, "%s(): DeviceID = 0x%X, DeviceRev = 0x%X.\n", __FUNCTION__, deviceID, deviceRev);
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if((AMBPEX8_DEVID != deviceID) &&
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(ADP201X1AMB_DEVID != deviceID) &&
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(AMBPEX5_DEVID != deviceID) &&
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(AMBPEXARM_DEVID != deviceID) &&
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(AMBFMC114V_DEVID != deviceID)) {
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dbg_msg(dbg_trace, "%s(): Unsupported device id: 0x%X.\n", __FUNCTION__, deviceID);
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return -ENODEV;
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}
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temp = ReadOperationWordReg(brd, PEMAINadr_PLD_VER);
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temp = ReadOperationWordReg(brd, PEMAINadr_PLD_VER);
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dbg_msg(dbg_trace, "%s(): PldVER = 0x%X.\n", __FUNCTION__, temp);
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dbg_msg(dbg_trace, "%s(): PldVER = 0x%X.\n", __FUNCTION__, temp);
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Line 125... |
}
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}
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}
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}
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dbg_msg(dbg_trace, "%s(): m_DmaChanMask = 0x%X\n", __FUNCTION__, brd->m_DmaChanMask);
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dbg_msg(dbg_trace, "%s(): m_DmaChanMask = 0x%X\n", __FUNCTION__, brd->m_DmaChanMask);
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// подготовим к работе ПЛИС ADM
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// подготовим к работе ПЛИС ADM
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dbg_msg(dbg_trace, "%s(): Prepare ADM PLD.\n", __FUNCTION__);
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dbg_msg(dbg_trace, "%s(): Prepare ADM PLD.\n", __FUNCTION__);
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WriteOperationWordReg(brd,PEMAINadr_BRD_MODE, 0);
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WriteOperationWordReg(brd,PEMAINadr_BRD_MODE, 0);
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ToPause(100); // pause ~ 100 msec
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ToPause(100); // pause ~ 100 msec
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for(i = 0; i < 10; i++)
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for(i = 0; i < 10; i++)
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Line 444... |
//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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int DmaEnable(struct pex_device *brd, u32 AdmNumber, u32 TetrNumber)
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int DmaEnable(struct pex_device *brd, u32 AdmNumber, u32 TetrNumber)
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{
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{
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int Status = 0;
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int Status = 0;
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u32 Value = 0;
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//u32 Value = 0;
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Status = ReadRegData(brd, AdmNumber, TetrNumber, 0, &Value);
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//Status = ReadRegData(brd, AdmNumber, TetrNumber, 0, &Value);
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if(Status != 0) return Status;
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//if(Status != 0) return Status;
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Value |= 0x8; // DRQ enable
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//Value |= 0x8; // DRQ enable
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Status = WriteRegData(brd, AdmNumber, TetrNumber, 0, Value);
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//Status = WriteRegData(brd, AdmNumber, TetrNumber, 0, Value);
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//err_msg(err_trace, "%s: MODE0 = 0x%X.\n", __FUNCTION__, Value);
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//err_msg(err_trace, "%s: MODE0 = 0x%X.\n", __FUNCTION__, Value);
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return Status;
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return Status;
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}
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}
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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int DmaDisable(struct pex_device *brd, u32 AdmNumber, u32 TetrNumber)
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int DmaDisable(struct pex_device *brd, u32 AdmNumber, u32 TetrNumber)
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{
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{
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int Status = 0;
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int Status = 0;
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u32 Value = 0;
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//u32 Value = 0;
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Status = ReadRegData(brd, AdmNumber, TetrNumber, 0, &Value);
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//Status = ReadRegData(brd, AdmNumber, TetrNumber, 0, &Value);
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if(Status != 0) return Status;
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//if(Status != 0) return Status;
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Value &= 0xfff7; // DRQ disable
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//Value &= 0xfff7; // DRQ disable
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Status = WriteRegData(brd, AdmNumber, TetrNumber, 0, Value);
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//Status = WriteRegData(brd, AdmNumber, TetrNumber, 0, Value);
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return Status;
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return Status;
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}
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}
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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Line 602... |
if(brd->m_DmaChanEnbl[i])
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if(brd->m_DmaChanEnbl[i])
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enbl = 1;
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enbl = 1;
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brd->m_DmaIrqEnbl = enbl;
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brd->m_DmaIrqEnbl = enbl;
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tetr_num = GetTetrNum(brd->m_DmaChannel[NumberOfChannel]);
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tetr_num = GetTetrNum(brd->m_DmaChannel[NumberOfChannel]);
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Status = DmaDisable(brd, 0, tetr_num);
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//Status = DmaDisable(brd, 0, tetr_num);
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CompleteDmaTransfer(brd->m_DmaChannel[NumberOfChannel]);
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CompleteDmaTransfer(brd->m_DmaChannel[NumberOfChannel]);
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return Status;
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return Status;
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}
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}
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