| Line 34... |
Line 34... |
use UNISIM.VComponents.all;
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use UNISIM.VComponents.all;
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entity Regs_Group is
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entity Regs_Group is
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port (
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port (
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-- DCB protocol interface
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-- -- DCB protocol interface
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protocol_link_act : IN std_logic_vector(2-1 downto 0);
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-- protocol_link_act : IN std_logic_vector(2-1 downto 0);
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protocol_rst : OUT std_logic;
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-- protocol_rst : OUT std_logic;
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--
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-- Fabric side: CTL Rx
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-- -- Fabric side: CTL Rx
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ctl_rv : OUT std_logic;
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-- ctl_rv : OUT std_logic;
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ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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-- ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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--
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-- Fabric side: CTL Tx
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-- -- Fabric side: CTL Tx
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ctl_ttake : OUT std_logic;
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-- ctl_ttake : OUT std_logic;
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ctl_tv : IN std_logic;
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-- ctl_tv : IN std_logic;
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ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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-- ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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ctl_tstop : OUT std_logic;
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-- ctl_tstop : OUT std_logic;
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--
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ctl_reset : OUT std_logic;
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-- ctl_reset : OUT std_logic;
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ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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-- ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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--
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-- Fabric side: DLM Rx
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-- -- Fabric side: DLM Rx
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dlm_tv : OUT std_logic;
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-- dlm_tv : OUT std_logic;
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dlm_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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-- dlm_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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--
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-- Fabric side: DLM Tx
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-- -- Fabric side: DLM Tx
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dlm_rv : IN std_logic;
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-- dlm_rv : IN std_logic;
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dlm_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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-- dlm_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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-- Event Buffer status + reset
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-- Event Buffer status + reset
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eb_FIFO_Status : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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eb_FIFO_Status : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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eb_FIFO_Rst : OUT std_logic;
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eb_FIFO_Rst : OUT std_logic;
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eb_FIFO_ow : IN std_logic;
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eb_FIFO_ow : IN std_logic;
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| Line 153... |
Line 153... |
-- Tx module reset
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-- Tx module reset
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Tx_Reset : OUT std_logic;
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Tx_Reset : OUT std_logic;
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-- to Interrupts Module
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-- to Interrupts Module
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Sys_IRQ : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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Sys_IRQ : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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DAQ_irq : IN std_logic;
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-- DAQ_irq : IN std_logic;
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CTL_irq : IN std_logic;
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-- CTL_irq : IN std_logic;
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DLM_irq : IN std_logic;
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-- DLM_irq : IN std_logic;
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-- System error and info
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-- System error and info
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Tx_TimeOut : IN std_logic;
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Tx_TimeOut : IN std_logic;
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Tx_eb_TimeOut : IN std_logic;
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Tx_eb_TimeOut : IN std_logic;
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Msg_Routing : OUT std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
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Msg_Routing : OUT std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
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| Line 172... |
Line 172... |
IG_Latency : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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IG_Latency : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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IG_Num_Assert : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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IG_Num_Assert : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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IG_Num_Deassert : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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IG_Num_Deassert : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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IG_Asserting : IN std_logic;
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IG_Asserting : IN std_logic;
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-- Data generator control
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-- -- Data generator control
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DG_is_Running : IN std_logic;
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-- DG_is_Running : IN std_logic;
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DG_Reset : OUT std_logic;
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-- DG_Reset : OUT std_logic;
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DG_Mask : OUT std_logic;
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-- DG_Mask : OUT std_logic;
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-- Clock and reset
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-- Clock and reset
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trn_clk : IN std_logic;
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trn_clk : IN std_logic;
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trn_lnk_up_n : IN std_logic;
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trn_lnk_up_n : IN std_logic;
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trn_reset_n : IN std_logic
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trn_reset_n : IN std_logic
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| Line 188... |
Line 188... |
end Regs_Group;
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end Regs_Group;
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architecture Behavioral of Regs_Group is
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architecture Behavioral of Regs_Group is
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type icapStates is ( icapST_Reset
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, icapST_Idle
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, icapST_Access
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, icapST_Abort
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);
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-- State variables of ICAP
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signal FSM_icap : icapStates;
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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signal Regs_WrDin_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal Regs_WrDin_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal Regs_WrAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
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signal Regs_WrAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
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signal Regs_WrMask_i : std_logic_vector(2-1 downto 0);
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signal Regs_WrMask_i : std_logic_vector(2-1 downto 0);
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| Line 246... |
Line 236... |
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-- Register read mux signals
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-- Register read mux signals
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signal Reg_RdMuxer_Hi : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
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signal Reg_RdMuxer_Hi : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
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signal Reg_RdMuxer_Lo : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
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signal Reg_RdMuxer_Lo : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
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-- Optical Link status
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-- -- Optical Link status
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signal Opto_Link_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- signal Opto_Link_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal Opto_Link_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- signal Opto_Link_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal Opto_Link_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- signal Opto_Link_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- Event Buffer
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-- Event Buffer
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signal eb_FIFO_Status_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal eb_FIFO_Status_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal eb_FIFO_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal eb_FIFO_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal eb_FIFO_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal eb_FIFO_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal eb_FIFO_Rst_i : std_logic;
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signal eb_FIFO_Rst_i : std_logic;
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| Line 304... |
Line 294... |
signal Sys_Int_Enable_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal Sys_Int_Enable_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal Sys_Int_Enable_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal Sys_Int_Enable_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal Sys_Int_Enable_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal Sys_Int_Enable_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- Data generator control
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-- -- Data generator control
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signal DG_Reset_i : std_logic;
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-- signal DG_Reset_i : std_logic;
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signal DG_Mask_i : std_logic;
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-- signal DG_Mask_i : std_logic;
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signal DG_is_Available : std_logic;
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-- signal DG_is_Available : std_logic;
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signal DG_Rst_Counter : std_logic_vector(8-1 downto 0);
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-- signal DG_Rst_Counter : std_logic_vector(8-1 downto 0);
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signal DG_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- signal DG_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal DG_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- signal DG_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal DG_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- signal DG_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- General Control and Status
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-- General Control and Status
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signal Sys_Error_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal Sys_Error_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal Sys_Error_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal Sys_Error_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal Sys_Error_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal Sys_Error_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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| Line 470... |
Line 460... |
signal dlm_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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signal dlm_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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begin
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begin
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DG_is_Available <= '0';
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-- DG_is_Available <= '0';
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-- protocol interface reset
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-- -- protocol interface reset
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protocol_rst <= protocol_rst_i;
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-- protocol_rst <= protocol_rst_i;
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--
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ctl_rv <= ctl_rv_i;
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-- ctl_rv <= ctl_rv_i;
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ctl_rd <= ctl_rd_i;
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-- ctl_rd <= ctl_rd_i;
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--
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ctl_ttake <= ctl_ttake_i;
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-- ctl_ttake <= ctl_ttake_i;
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ctl_tstop <= ctl_tstop_i;
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-- ctl_tstop <= ctl_tstop_i;
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ctl_reset <= ctl_reset_i;
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-- ctl_reset <= ctl_reset_i;
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--
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ctl_tstop_i <= '0'; -- ???
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-- ctl_tstop_i <= '0'; -- ???
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--
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dlm_tv <= dlm_tv_i;
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-- dlm_tv <= dlm_tv_i;
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dlm_td <= dlm_td_i;
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-- dlm_td <= dlm_td_i;
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-- Data generator control
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-- -- Data generator control
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DG_Reset <= DG_Reset_i;
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-- DG_Reset <= DG_Reset_i;
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DG_Mask <= DG_Mask_i;
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-- DG_Mask <= DG_Mask_i;
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-- Event buffer reset
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-- Event buffer reset
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eb_FIFO_Rst <= eb_FIFO_Rst_i;
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eb_FIFO_Rst <= eb_FIFO_Rst_i;
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-- MRd channel reset
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-- MRd channel reset
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| Line 702... |
Line 692... |
Regs_WrEnB_r2 <= Regs_WrEnB_r1;
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Regs_WrEnB_r2 <= Regs_WrEnB_r1;
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end if;
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end if;
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end process;
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end process;
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-- ----------------------------------------------
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---- ----------------------------------------------
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-- Synchronous Delay : Opto_Link_Status
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---- Synchronous Delay : Opto_Link_Status
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--
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----
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Synch_Delay_Opto_Link_Status:
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-- Synch_Delay_Opto_Link_Status:
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process ( trn_clk )
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-- process ( trn_clk )
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begin
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-- begin
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if trn_clk'event and trn_clk = '1' then
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-- if trn_clk'event and trn_clk = '1' then
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Opto_Link_Status_i(C_DBUS_WIDTH-1 downto 2) <= (OTHERS=>'0');
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-- Opto_Link_Status_i(C_DBUS_WIDTH-1 downto 2) <= (OTHERS=>'0');
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Opto_Link_Status_i(2-1 downto 0) <= protocol_link_act;
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-- Opto_Link_Status_i(2-1 downto 0) <= protocol_link_act;
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end if;
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-- end if;
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end process;
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-- end process;
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-- ----------------------------------------------
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-- ----------------------------------------------
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-- Synchronous Delay : eb_FIFO_Status
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-- Synchronous Delay : eb_FIFO_Status
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--
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--
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Synch_Delay_eb_FIFO_Status:
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Synch_Delay_eb_FIFO_Status:
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| Line 1010... |
Line 1000... |
end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- -----------------------------------------------
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---- -----------------------------------------------
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-- Synchronous Registered: DG_Reset_i
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---- Synchronous Registered: DG_Reset_i
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SysReg_DGen_Reset:
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-- SysReg_DGen_Reset:
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process ( trn_clk, trn_lnk_up_n)
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-- process ( trn_clk, trn_lnk_up_n)
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begin
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-- begin
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if trn_lnk_up_n = '1' then
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-- if trn_lnk_up_n = '1' then
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DG_Reset_i <= '1';
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-- DG_Reset_i <= '1';
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DG_Rst_Counter <= (OTHERS=>'0');
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-- DG_Rst_Counter <= (OTHERS=>'0');
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elsif trn_clk'event and trn_clk = '1' then
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if DG_Rst_Counter=X"FF" then
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DG_Rst_Counter <= DG_Rst_Counter;
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else
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DG_Rst_Counter <= DG_Rst_Counter + '1';
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end if;
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if DG_Rst_Counter(7)='0' then
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DG_Reset_i <= '1';
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elsif Regs_WrEn_r2='1'
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and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
|
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then
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DG_Reset_i <= Command_is_Reset_Hi;
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elsif Regs_WrEn_r2='1'
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and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
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then
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DG_Reset_i <= Command_is_Reset_Lo;
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else
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DG_Reset_i <= '0';
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end if;
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end if;
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end process;
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-- -----------------------------------------------
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-- Synchronous Registered: DG_Mask_i
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SysReg_DGen_Mask:
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process ( trn_clk, trn_lnk_up_n)
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begin
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if trn_lnk_up_n = '1' then
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DG_Mask_i <= '0';
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elsif trn_clk'event and trn_clk = '1' then
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if Regs_WrEn_r2='1'
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and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
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then
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DG_Mask_i <= Regs_WrDin_r2(32+CINT_BIT_DG_MASK);
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elsif Regs_WrEn_r2='1'
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and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
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then
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DG_Mask_i <= Regs_WrDin_r2(CINT_BIT_DG_MASK);
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else
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DG_Mask_i <= DG_Mask_i;
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end if;
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end if;
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end process;
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--------------------------------------------------------------------------
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-- Data generator status
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--
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--
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Synch_DG_Status_i:
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-- elsif trn_clk'event and trn_clk = '1' then
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process ( trn_clk, DG_Reset_i )
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--
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begin
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-- if DG_Rst_Counter=X"FF" then
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if DG_Reset_i = '1' then
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-- DG_Rst_Counter <= DG_Rst_Counter;
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DG_Status_i <= (OTHERS=>'0');
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-- else
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elsif trn_clk'event and trn_clk = '1' then
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-- DG_Rst_Counter <= DG_Rst_Counter + '1';
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DG_Status_i(CINT_BIT_DG_MASK) <= DG_Mask_i;
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-- end if;
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DG_Status_i(CINT_BIT_DG_BUSY) <= DG_is_Running;
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--
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end if;
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-- if DG_Rst_Counter(7)='0' then
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end process;
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-- DG_Reset_i <= '1';
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-- elsif Regs_WrEn_r2='1'
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-- and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
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-- then
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-- DG_Reset_i <= Command_is_Reset_Hi;
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-- elsif Regs_WrEn_r2='1'
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-- and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
|
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-- then
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-- DG_Reset_i <= Command_is_Reset_Lo;
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-- else
|
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-- DG_Reset_i <= '0';
|
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-- end if;
|
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--
|
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-- end if;
|
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-- end process;
|
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--
|
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---- -----------------------------------------------
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---- Synchronous Registered: DG_Mask_i
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-- SysReg_DGen_Mask:
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-- process ( trn_clk, trn_lnk_up_n)
|
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-- begin
|
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-- if trn_lnk_up_n = '1' then
|
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-- DG_Mask_i <= '0';
|
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-- elsif trn_clk'event and trn_clk = '1' then
|
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--
|
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-- if Regs_WrEn_r2='1'
|
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-- and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
|
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-- then
|
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-- DG_Mask_i <= Regs_WrDin_r2(32+CINT_BIT_DG_MASK);
|
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-- elsif Regs_WrEn_r2='1'
|
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-- and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
|
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-- then
|
|
-- DG_Mask_i <= Regs_WrDin_r2(CINT_BIT_DG_MASK);
|
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-- else
|
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-- DG_Mask_i <= DG_Mask_i;
|
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-- end if;
|
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--
|
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-- end if;
|
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-- end process;
|
|
--
|
|
----------------------------------------------------------------------------
|
|
---- Data generator status
|
|
----
|
|
-- Synch_DG_Status_i:
|
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-- process ( trn_clk, DG_Reset_i )
|
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-- begin
|
|
-- if DG_Reset_i = '1' then
|
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-- DG_Status_i <= (OTHERS=>'0');
|
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-- elsif trn_clk'event and trn_clk = '1' then
|
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-- DG_Status_i(CINT_BIT_DG_MASK) <= DG_Mask_i;
|
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-- DG_Status_i(CINT_BIT_DG_BUSY) <= DG_is_Running;
|
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-- end if;
|
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-- end process;
|
|
|
-- -----------------------------------------------
|
-- -----------------------------------------------
|
-- Synchronous Registered: IG_Control_i
|
-- Synchronous Registered: IG_Control_i
|
SysReg_IntGen_Control:
|
SysReg_IntGen_Control:
|
process ( trn_clk, trn_lnk_up_n)
|
process ( trn_clk, trn_lnk_up_n)
|
| Line 1146... |
Line 1136... |
end process;
|
end process;
|
|
|
|
|
|
|
|
|
-- ------------------------------------------------------
|
---- ------------------------------------------------------
|
-- Protocol CTL interface
|
---- Protocol CTL interface
|
-- ------------------------------------------------------
|
---- ------------------------------------------------------
|
|
--
|
-- -------------------------------------------------------
|
---- -------------------------------------------------------
|
-- Synchronous Registered: ctl_rd
|
---- Synchronous Registered: ctl_rd
|
Syn_CTL_rd:
|
-- Syn_CTL_rd:
|
process ( trn_clk, trn_lnk_up_n)
|
-- process ( trn_clk, trn_lnk_up_n)
|
begin
|
-- begin
|
if trn_lnk_up_n = '1' then
|
-- if trn_lnk_up_n = '1' then
|
ctl_rd_i <= (OTHERS => '0');
|
-- ctl_rd_i <= (OTHERS => '0');
|
ctl_rv_i <= '0';
|
-- ctl_rv_i <= '0';
|
elsif trn_clk'event and trn_clk = '1' then
|
-- elsif trn_clk'event and trn_clk = '1' then
|
|
--
|
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_CTL_CLASS)='1' then
|
-- if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_CTL_CLASS)='1' then
|
ctl_rd_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
|
-- ctl_rd_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
|
ctl_rv_i <= '1';
|
-- ctl_rv_i <= '1';
|
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_CTL_CLASS)='1' then
|
-- elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_CTL_CLASS)='1' then
|
ctl_rd_i <= Regs_WrDin_r2(32-1 downto 0);
|
-- ctl_rd_i <= Regs_WrDin_r2(32-1 downto 0);
|
ctl_rv_i <= '1';
|
-- ctl_rv_i <= '1';
|
else
|
-- else
|
ctl_rd_i <= ctl_rd_i;
|
-- ctl_rd_i <= ctl_rd_i;
|
ctl_rv_i <= '0';
|
-- ctl_rv_i <= '0';
|
end if;
|
-- end if;
|
|
--
|
end if;
|
-- end if;
|
end process;
|
-- end process;
|
|
--
|
|
--
|
-- -----------------------------------------------
|
---- -----------------------------------------------
|
-- Synchronous Registered: ctl_reset
|
---- Synchronous Registered: ctl_reset
|
SysReg_ctl_reset:
|
-- SysReg_ctl_reset:
|
process ( trn_clk, trn_lnk_up_n)
|
-- process ( trn_clk, trn_lnk_up_n)
|
begin
|
-- begin
|
if trn_lnk_up_n = '1' then
|
-- if trn_lnk_up_n = '1' then
|
ctl_reset_i <= '1';
|
-- ctl_reset_i <= '1';
|
|
--
|
elsif trn_clk'event and trn_clk = '1' then
|
-- elsif trn_clk'event and trn_clk = '1' then
|
|
--
|
if Regs_WrEn_r2='1'
|
-- if Regs_WrEn_r2='1'
|
and Reg_WrMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
|
-- and Reg_WrMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
|
then
|
-- then
|
ctl_reset_i <= Command_is_Reset_Hi;
|
-- ctl_reset_i <= Command_is_Reset_Hi;
|
elsif Regs_WrEn_r2='1'
|
-- elsif Regs_WrEn_r2='1'
|
and Reg_WrMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
|
-- and Reg_WrMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
|
then
|
-- then
|
ctl_reset_i <= Command_is_Reset_Lo;
|
-- ctl_reset_i <= Command_is_Reset_Lo;
|
else
|
-- else
|
ctl_reset_i <= '0';
|
-- ctl_reset_i <= '0';
|
end if;
|
-- end if;
|
|
--
|
end if;
|
-- end if;
|
end process;
|
-- end process;
|
|
--
|
|
--
|
|
--
|
-- -------------------------------------------------------
|
---- -------------------------------------------------------
|
-- Synchronous Registered: ctl_td
|
---- Synchronous Registered: ctl_td
|
-- ++++++++++++ INT triggering ++++++++++++++++++
|
---- ++++++++++++ INT triggering ++++++++++++++++++
|
Syn_CTL_td:
|
-- Syn_CTL_td:
|
process ( trn_clk, trn_lnk_up_n)
|
-- process ( trn_clk, trn_lnk_up_n)
|
begin
|
-- begin
|
if trn_lnk_up_n = '1' then
|
-- if trn_lnk_up_n = '1' then
|
ctl_td_r <= (OTHERS => '0');
|
-- ctl_td_r <= (OTHERS => '0');
|
elsif trn_clk'event and trn_clk = '1' then
|
-- elsif trn_clk'event and trn_clk = '1' then
|
|
--
|
if ctl_tv='1' then
|
-- if ctl_tv='1' then
|
ctl_td_r <= ctl_td;
|
-- ctl_td_r <= ctl_td;
|
else
|
-- else
|
ctl_td_r <= ctl_td_r;
|
-- ctl_td_r <= ctl_td_r;
|
end if;
|
-- end if;
|
|
--
|
end if;
|
-- end if;
|
end process;
|
-- end process;
|
|
--
|
|
--
|
|
--
|
-- ------------------------------------------------------
|
---- ------------------------------------------------------
|
-- Protocol DLM interface
|
---- Protocol DLM interface
|
-- ------------------------------------------------------
|
---- ------------------------------------------------------
|
|
--
|
-- -------------------------------------------------------
|
---- -------------------------------------------------------
|
-- Synchronous Registered: dlm_td
|
---- Synchronous Registered: dlm_td
|
Syn_DLM_td:
|
-- Syn_DLM_td:
|
process ( trn_clk, trn_lnk_up_n)
|
-- process ( trn_clk, trn_lnk_up_n)
|
begin
|
-- begin
|
if trn_lnk_up_n = '1' then
|
-- if trn_lnk_up_n = '1' then
|
dlm_td_i <= (OTHERS => '0');
|
-- dlm_td_i <= (OTHERS => '0');
|
dlm_tv_i <= '0';
|
-- dlm_tv_i <= '0';
|
elsif trn_clk'event and trn_clk = '1' then
|
-- elsif trn_clk'event and trn_clk = '1' then
|
|
--
|
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DLM_CLASS)='1' then
|
-- if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DLM_CLASS)='1' then
|
dlm_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
|
-- dlm_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
|
dlm_tv_i <= '1';
|
-- dlm_tv_i <= '1';
|
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DLM_CLASS)='1' then
|
-- elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DLM_CLASS)='1' then
|
dlm_td_i <= Regs_WrDin_r2(32-1 downto 0);
|
-- dlm_td_i <= Regs_WrDin_r2(32-1 downto 0);
|
dlm_tv_i <= '1';
|
-- dlm_tv_i <= '1';
|
else
|
-- else
|
dlm_td_i <= dlm_td_i;
|
-- dlm_td_i <= dlm_td_i;
|
dlm_tv_i <= '0';
|
-- dlm_tv_i <= '0';
|
end if;
|
-- end if;
|
|
--
|
end if;
|
-- end if;
|
end process;
|
-- end process;
|
|
--
|
|
--
|
-- -------------------------------------------------------
|
---- -------------------------------------------------------
|
-- Synchronous Registered: dlm_rd
|
---- Synchronous Registered: dlm_rd
|
-- ++++++++++++ INT triggering ++++++++++++++++++
|
---- ++++++++++++ INT triggering ++++++++++++++++++
|
Syn_DLM_rd:
|
-- Syn_DLM_rd:
|
process ( trn_clk, trn_lnk_up_n)
|
-- process ( trn_clk, trn_lnk_up_n)
|
begin
|
-- begin
|
if trn_lnk_up_n = '1' then
|
-- if trn_lnk_up_n = '1' then
|
dlm_rd_r <= (OTHERS => '0');
|
-- dlm_rd_r <= (OTHERS => '0');
|
elsif trn_clk'event and trn_clk = '1' then
|
-- elsif trn_clk'event and trn_clk = '1' then
|
|
--
|
if dlm_rv='1' then
|
-- if dlm_rv='1' then
|
dlm_rd_r <= dlm_rd;
|
-- dlm_rd_r <= dlm_rd;
|
else
|
-- else
|
dlm_rd_r <= dlm_rd_r;
|
-- dlm_rd_r <= dlm_rd_r;
|
end if;
|
-- end if;
|
|
--
|
end if;
|
-- end if;
|
end process;
|
-- end process;
|
|
|
|
|
-- ------------------------------------------------------
|
-- ------------------------------------------------------
|
-- DMA Upstream Registers
|
-- DMA Upstream Registers
|
-- ------------------------------------------------------
|
-- ------------------------------------------------------
|
| Line 2300... |
Line 2290... |
DMA_ds_Transf_Bytes_i <= DMA_ds_Transf_Bytes_i;
|
DMA_ds_Transf_Bytes_i <= DMA_ds_Transf_Bytes_i;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
---- -------------------------------------------------------
|
|
---- Synchronous Registers: icap_Write_i
|
|
-- RxTrn_icap_Write:
|
|
-- process ( trn_clk, trn_lnk_up_n)
|
|
-- begin
|
|
-- if trn_lnk_up_n = '1' then
|
|
-- icap_CLK <= '0';
|
|
-- icap_I <= (OTHERS => '0');
|
|
-- icap_Write <= '1';
|
|
-- icap_CE <= '1';
|
|
-- FSM_icap <= icapST_Reset;
|
|
--
|
|
-- elsif trn_clk'event and trn_clk = '1' then
|
|
--
|
|
-- case FSM_icap is
|
|
--
|
|
-- when icapST_Reset =>
|
|
-- icap_CLK <= '0';
|
|
-- icap_I <= (OTHERS => '0');
|
|
-- icap_Write <= '1';
|
|
-- icap_CE <= '1';
|
|
-- FSM_icap <= icapST_Idle;
|
|
--
|
|
-- when icapST_Idle =>
|
|
--
|
|
-- if Regs_WrEn_r2='1' and Reg_WrMuxer(CINT_ADDR_ICAP)='1' then
|
|
-- icap_CLK <= '1';
|
|
-- icap_I <= Regs_WrDin_r2;
|
|
-- icap_Write <= '0';
|
|
-- icap_CE <= '0';
|
|
-- FSM_icap <= icapST_Access;
|
|
-- elsif Reg_RdMuxer(CINT_ADDR_ICAP)='1' then
|
|
-- icap_CLK <= '1';
|
|
-- icap_I <= icap_I;
|
|
-- icap_Write <= '1';
|
|
-- icap_CE <= '0';
|
|
-- FSM_icap <= icapST_Access;
|
|
-- else
|
|
-- icap_CLK <= icap_CLK;
|
|
-- icap_I <= icap_I;
|
|
-- icap_Write <= icap_Write;
|
|
-- icap_CE <= icap_CE;
|
|
-- FSM_icap <= icapST_Idle;
|
|
-- end if;
|
|
--
|
|
--
|
|
-- when icapST_Access =>
|
|
-- icap_CLK <= '1';
|
|
-- icap_I <= icap_I;
|
|
-- icap_Write <= icap_Write;
|
|
-- icap_CE <= icap_CE;
|
|
-- FSM_icap <= icapST_Abort;
|
|
--
|
|
-- when icapST_Abort =>
|
|
-- icap_CLK <= '0';
|
|
-- icap_I <= icap_I;
|
|
-- icap_Write <= icap_Write;
|
|
-- icap_CE <= icap_CE;
|
|
-- FSM_icap <= icapST_Idle;
|
|
--
|
|
-- when Others =>
|
|
-- icap_CLK <= '0';
|
|
-- icap_I <= (OTHERS => '0');
|
|
-- icap_Write <= '1';
|
|
-- icap_CE <= '1';
|
|
-- FSM_icap <= icapST_Idle;
|
|
--
|
|
-- end case;
|
|
--
|
|
-- end if;
|
|
-- end process;
|
|
--
|
|
|
|
|
|
----------------------------------------------------------
|
----------------------------------------------------------
|
--------------- Tx reading registers -------------------
|
--------------- Tx reading registers -------------------
|
----------------------------------------------------------
|
----------------------------------------------------------
|
| Line 2424... |
Line 2342... |
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
----------------------------------------------------------
|
------------------------------------------------------------
|
-- Synch Register: CTL_TTake
|
---- Synch Register: CTL_TTake
|
|
----
|
|
-- Syn_CTL_ttake:
|
|
-- process ( trn_clk, trn_lnk_up_n)
|
|
-- begin
|
|
-- if trn_lnk_up_n = '1' then
|
|
-- ctl_ttake_i <= '0';
|
|
-- ctl_t_read_Hi_r1 <= '0';
|
|
-- ctl_t_read_Lo_r1 <= '0';
|
|
-- CTL_read_counter <= (OTHERS=>'0');
|
--
|
--
|
Syn_CTL_ttake:
|
-- elsif trn_clk'event and trn_clk = '1' then
|
process ( trn_clk, trn_lnk_up_n)
|
-- ctl_t_read_Hi_r1 <= Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS);
|
begin
|
-- ctl_t_read_Lo_r1 <= Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS);
|
if trn_lnk_up_n = '1' then
|
-- ctl_ttake_i <= (Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Hi_r1)
|
ctl_ttake_i <= '0';
|
-- or (Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Lo_r1)
|
ctl_t_read_Hi_r1 <= '0';
|
-- ;
|
ctl_t_read_Lo_r1 <= '0';
|
-- if ctl_reset_i='1' then
|
CTL_read_counter <= (OTHERS=>'0');
|
-- CTL_read_counter <= (OTHERS=>'0');
|
|
-- else
|
elsif trn_clk'event and trn_clk = '1' then
|
-- CTL_read_counter <= CTL_read_counter + ctl_ttake_i;
|
ctl_t_read_Hi_r1 <= Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS);
|
-- end if;
|
ctl_t_read_Lo_r1 <= Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS);
|
|
ctl_ttake_i <= (Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Hi_r1)
|
|
or (Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Lo_r1)
|
|
;
|
|
if ctl_reset_i='1' then
|
|
CTL_read_counter <= (OTHERS=>'0');
|
|
else
|
|
CTL_read_counter <= CTL_read_counter + ctl_ttake_i;
|
|
end if;
|
|
|
|
end if;
|
|
end process;
|
|
|
|
----------------------------------------------------------
|
|
-- Synch Register: class_CTL_Status
|
|
--
|
--
|
Syn_class_CTL_Status:
|
-- end if;
|
process ( trn_clk, trn_lnk_up_n)
|
-- end process;
|
begin
|
--
|
if trn_lnk_up_n = '1' then
|
------------------------------------------------------------
|
class_CTL_Status_i <= (OTHERS=>'0');
|
---- Synch Register: class_CTL_Status
|
|
----
|
elsif trn_clk'event and trn_clk = '1' then
|
-- Syn_class_CTL_Status:
|
class_CTL_Status_i(C_DBUS_WIDTH/2-1 downto 0) <= ctl_status;
|
-- process ( trn_clk, trn_lnk_up_n)
|
|
-- begin
|
end if;
|
-- if trn_lnk_up_n = '1' then
|
end process;
|
-- class_CTL_Status_i <= (OTHERS=>'0');
|
|
--
|
|
-- elsif trn_clk'event and trn_clk = '1' then
|
|
-- class_CTL_Status_i(C_DBUS_WIDTH/2-1 downto 0) <= ctl_status;
|
|
--
|
|
-- end if;
|
|
-- end process;
|
|
|
|
|
-- -------------------------------------------------------
|
-- -------------------------------------------------------
|
--
|
--
|
Sys_Int_Status_i <= (
|
Sys_Int_Status_i <= (
|
CINT_BIT_DLM_IN_ISR => DLM_irq ,
|
-- CINT_BIT_DLM_IN_ISR => DLM_irq ,
|
CINT_BIT_CTL_IN_ISR => CTL_irq ,
|
-- CINT_BIT_CTL_IN_ISR => CTL_irq ,
|
CINT_BIT_DAQ_IN_ISR => DAQ_irq ,
|
-- CINT_BIT_DAQ_IN_ISR => DAQ_irq ,
|
|
|
CINT_BIT_DSTOUT_IN_ISR => DMA_ds_Tout ,
|
CINT_BIT_DSTOUT_IN_ISR => DMA_ds_Tout ,
|
CINT_BIT_USTOUT_IN_ISR => DMA_us_Tout ,
|
CINT_BIT_USTOUT_IN_ISR => DMA_us_Tout ,
|
|
|
CINT_BIT_INTGEN_IN_ISR => IG_Asserting,
|
CINT_BIT_INTGEN_IN_ISR => IG_Asserting,
|
| Line 2810... |
Line 2728... |
<= cfg_dcommand;
|
<= cfg_dcommand;
|
General_Status_i(CINT_BIT_LWIDTH_IN_GSR_TOP downto CINT_BIT_LWIDTH_IN_GSR_BOT)
|
General_Status_i(CINT_BIT_LWIDTH_IN_GSR_TOP downto CINT_BIT_LWIDTH_IN_GSR_BOT)
|
<= pcie_link_width;
|
<= pcie_link_width;
|
General_Status_i(CINT_BIT_ICAP_BUSY_IN_GSR)
|
General_Status_i(CINT_BIT_ICAP_BUSY_IN_GSR)
|
<= icap_Busy;
|
<= icap_Busy;
|
General_Status_i(CINT_BIT_DG_AVAIL_IN_GSR)
|
-- General_Status_i(CINT_BIT_DG_AVAIL_IN_GSR)
|
<= DG_is_Available;
|
-- <= DG_is_Available;
|
General_Status_i(CINT_BIT_LINK_ACT_IN_GSR+1 downto CINT_BIT_LINK_ACT_IN_GSR)
|
-- General_Status_i(CINT_BIT_LINK_ACT_IN_GSR+1 downto CINT_BIT_LINK_ACT_IN_GSR)
|
<= protocol_link_act;
|
-- <= protocol_link_act;
|
|
|
-- General_Status_i(8) <= CTL_read_counter(6-1); ---- DEBUG !!!
|
-- General_Status_i(8) <= CTL_read_counter(6-1); ---- DEBUG !!!
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
| Line 2868... |
Line 2786... |
|
|
eb_FIFO_Status_o_Lo(32-1 downto 0)
|
eb_FIFO_Status_o_Lo(32-1 downto 0)
|
<= eb_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_EB_STACON)='1'
|
<= eb_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_EB_STACON)='1'
|
else (Others=>'0');
|
else (Others=>'0');
|
|
|
--------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------
|
-- Optical Link Status
|
-- -- Optical Link Status
|
--------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------
|
Opto_Link_Status_o_Hi(32-1 downto 0)
|
-- Opto_Link_Status_o_Hi(32-1 downto 0)
|
<= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_PROTOCOL_STACON)='1'
|
-- <= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_PROTOCOL_STACON)='1'
|
else (Others=>'0');
|
-- else (Others=>'0');
|
|
--
|
Opto_link_Status_o_Lo(32-1 downto 0)
|
-- Opto_link_Status_o_Lo(32-1 downto 0)
|
<= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_PROTOCOL_STACON)='1'
|
-- <= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_PROTOCOL_STACON)='1'
|
else (Others=>'0');
|
-- else (Others=>'0');
|
|
--
|
--------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------
|
-- Class CTL status
|
-- -- Class CTL status
|
--------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------
|
class_CTL_Status_o_Hi(32-1 downto 0)
|
-- class_CTL_Status_o_Hi(32-1 downto 0)
|
<= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
|
-- <= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
|
else (Others=>'0');
|
-- else (Others=>'0');
|
|
--
|
class_CTL_Status_o_Lo(32-1 downto 0)
|
-- class_CTL_Status_o_Lo(32-1 downto 0)
|
<= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
|
-- <= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
|
else (Others=>'0');
|
-- else (Others=>'0');
|
|
--
|
--------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------
|
-- Data generator Status
|
-- -- Data generator Status
|
--------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------
|
DG_Status_o_Hi(32-1 downto 0)
|
-- DG_Status_o_Hi(32-1 downto 0)
|
<= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
|
-- <= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
|
else (Others=>'0');
|
-- else (Others=>'0');
|
|
--
|
DG_Status_o_Lo(32-1 downto 0)
|
-- DG_Status_o_Lo(32-1 downto 0)
|
<= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
|
-- <= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
|
else (Others=>'0');
|
-- else (Others=>'0');
|
|
|
--------------------------------------------------------------------------
|
--------------------------------------------------------------------------
|
-- Hardware version
|
-- Hardware version
|
--------------------------------------------------------------------------
|
--------------------------------------------------------------------------
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HW_Version_o_Hi(32-1 downto 0)
|
HW_Version_o_Hi(32-1 downto 0)
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| Line 2959... |
Line 2877... |
|
|
or IG_Latency_o_Hi (32-1 downto 0)
|
or IG_Latency_o_Hi (32-1 downto 0)
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or IG_Num_Assert_o_Hi (32-1 downto 0)
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or IG_Num_Assert_o_Hi (32-1 downto 0)
|
or IG_Num_Deassert_o_Hi(32-1 downto 0)
|
or IG_Num_Deassert_o_Hi(32-1 downto 0)
|
|
|
or DG_Status_o_Hi (32-1 downto 0)
|
-- or DG_Status_o_Hi (32-1 downto 0)
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or class_CTL_Status_o_Hi (32-1 downto 0)
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-- or class_CTL_Status_o_Hi (32-1 downto 0)
|
|
|
-- or icap_O_o_Hi (32-1 downto 0)
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-- or icap_O_o_Hi (32-1 downto 0)
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or Opto_Link_Status_o_Hi (32-1 downto 0)
|
-- or Opto_Link_Status_o_Hi (32-1 downto 0)
|
or eb_FIFO_Status_o_Hi (32-1 downto 0)
|
or eb_FIFO_Status_o_Hi (32-1 downto 0)
|
or dlm_rd_o_Hi
|
-- or dlm_rd_o_Hi
|
or ctl_td_o_Hi
|
-- or ctl_td_o_Hi
|
;
|
;
|
|
|
|
|
Regs_RdQout_i(32-1 downto 0) <=
|
Regs_RdQout_i(32-1 downto 0) <=
|
HW_Version_o_Lo (32-1 downto 0)
|
HW_Version_o_Lo (32-1 downto 0)
|
| Line 3006... |
Line 2924... |
|
|
or IG_Latency_o_Lo (32-1 downto 0)
|
or IG_Latency_o_Lo (32-1 downto 0)
|
or IG_Num_Assert_o_Lo (32-1 downto 0)
|
or IG_Num_Assert_o_Lo (32-1 downto 0)
|
or IG_Num_Deassert_o_Lo(32-1 downto 0)
|
or IG_Num_Deassert_o_Lo(32-1 downto 0)
|
|
|
or DG_Status_o_Lo (32-1 downto 0)
|
-- or DG_Status_o_Lo (32-1 downto 0)
|
or class_CTL_Status_o_Lo (32-1 downto 0)
|
-- or class_CTL_Status_o_Lo (32-1 downto 0)
|
|
|
-- or icap_O_o_Lo(32-1 downto 0)
|
-- or icap_O_o_Lo(32-1 downto 0)
|
or Opto_Link_Status_o_Lo (32-1 downto 0)
|
-- or Opto_Link_Status_o_Lo (32-1 downto 0)
|
or eb_FIFO_Status_o_Lo (32-1 downto 0)
|
or eb_FIFO_Status_o_Lo (32-1 downto 0)
|
or dlm_rd_o_Lo
|
-- or dlm_rd_o_Lo
|
or ctl_td_o_Lo
|
-- or ctl_td_o_Lo
|
;
|
;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
-- -----------------------------------------------------------------------------
|
|
-- -- Implementation codes
|
|
-- -----------------------------------------------------------------------------
|
|
-- Gen_ICAP_width_8:
|
|
-- if C_ICAP_WIDTH=8 generate
|
|
--
|
|
-- ICAP_VIRTEX4_pcie :
|
|
-- ICAP_VIRTEX4
|
|
-- generic map (
|
|
-- ICAP_WIDTH => "X8" -- "X8" or "X32"
|
|
-- )
|
|
-- port map (
|
|
-- BUSY => icap_BUSY , -- Busy output
|
|
-- O => icap_O , -- 8-bit data output
|
|
-- CE => icap_CE , -- Clock enable input
|
|
-- CLK => icap_CLK , -- Clock input
|
|
-- I => icap_I , -- 8-bit data input
|
|
-- WRITE => icap_WRITE -- Write input
|
|
-- );
|
|
--
|
|
-- end generate;
|
|
--
|
|
-- Gen_ICAP_width_32:
|
|
-- if C_ICAP_WIDTH=32 generate
|
|
--
|
|
-- ICAP_VIRTEX4_pcie :
|
|
-- ICAP_VIRTEX4
|
|
-- generic map (
|
|
-- ICAP_WIDTH => "X32" -- "X8" or "X32"
|
|
-- )
|
|
-- port map (
|
|
-- BUSY => icap_BUSY , -- Busy output
|
|
-- O => icap_O , -- 32-bit data output
|
|
-- CE => icap_CE , -- Clock enable input
|
|
-- CLK => icap_CLK , -- Clock input
|
|
-- I => icap_I , -- 32-bit data input
|
|
-- WRITE => icap_WRITE -- Write input
|
|
-- );
|
|
--
|
|
-- end generate;
|
|
--
|
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
No newline at end of file
|
No newline at end of file
|
