| Line 143... |
Line 143... |
signal eb_FIFO_RdEn_Mask_rise_r3 : std_logic;
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signal eb_FIFO_RdEn_Mask_rise_r3 : std_logic;
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signal eb_FIFO_RdEn_Mask : std_logic;
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signal eb_FIFO_RdEn_Mask : std_logic;
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signal eb_FIFO_RdEn_Mask_r1 : std_logic;
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signal eb_FIFO_RdEn_Mask_r1 : std_logic;
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signal eb_FIFO_RdEn_Mask_r2 : std_logic;
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signal eb_FIFO_RdEn_Mask_r2 : std_logic;
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signal ebFIFO_Rd_1DW : std_logic;
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signal ebFIFO_Rd_1DW : std_logic;
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signal ebFIFO_Rd_1DW_r1 : std_logic;
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signal eb_FIFO_qout_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal eb_FIFO_qout_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal eb_FIFO_qout_shift : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal eb_FIFO_qout_shift : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal eb_FIFO_qout_swapped : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal eb_FIFO_qout_swapped : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- Memory data outputs
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-- Memory data outputs
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| Line 740... |
Line 741... |
process ( trn_clk )
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process ( trn_clk )
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begin
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begin
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if trn_clk'event and trn_clk = '1' then
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if trn_clk'event and trn_clk = '1' then
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mbuf_WE_i <= DDR_FIFO_Write_mbuf_r1
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mbuf_WE_i <= DDR_FIFO_Write_mbuf_r1
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or Regs_Write_mbuf_r2
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or Regs_Write_mbuf_r2
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or (eb_FIFO_Write_mbuf_r1 or (Shift_1st_QWord_k and eb_FIFO_RdEn_Mask_rise_r1))
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or (eb_FIFO_Write_mbuf_r1 or (Shift_1st_QWord_k
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and eb_FIFO_RdEn_Mask_rise_r1 and not ebFIFO_Rd_1DW_r1))
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;
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;
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end if;
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end if;
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end process;
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end process;
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| Line 777... |
Line 779... |
--
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--
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Synchron_Delay_eb_FIFO_qout:
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Synchron_Delay_eb_FIFO_qout:
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process ( trn_clk )
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process ( trn_clk )
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begin
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begin
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if trn_clk'event and trn_clk = '1' then
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if trn_clk'event and trn_clk = '1' then
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ebFIFO_Rd_1DW_r1 <= ebFIFO_Rd_1DW;
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eb_FIFO_RdEn_Mask_rise <= eb_FIFO_RdEn_Mask and not eb_FIFO_RdEn_Mask_r1;
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eb_FIFO_RdEn_Mask_rise <= eb_FIFO_RdEn_Mask and not eb_FIFO_RdEn_Mask_r1;
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eb_FIFO_RdEn_Mask_rise_r1 <= eb_FIFO_RdEn_Mask_rise;
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eb_FIFO_RdEn_Mask_rise_r1 <= eb_FIFO_RdEn_Mask_rise;
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eb_FIFO_RdEn_Mask_rise_r2 <= eb_FIFO_RdEn_Mask_rise_r1;
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eb_FIFO_RdEn_Mask_rise_r2 <= eb_FIFO_RdEn_Mask_rise_r1;
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eb_FIFO_qout_r1 <= eb_FIFO_qout_swapped;
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eb_FIFO_qout_r1 <= eb_FIFO_qout_swapped;
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eb_FIFO_qout_shift <= eb_FIFO_qout_r1(C_DBUS_WIDTH/2-1 downto 0)
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eb_FIFO_qout_shift <= eb_FIFO_qout_r1(C_DBUS_WIDTH/2-1 downto 0)
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