| Line 265... |
Line 265... |
-- signal mem_clk : std_logic;
|
-- signal mem_clk : std_logic;
|
|
|
-- -----------------------------------------------------------------------
|
-- -----------------------------------------------------------------------
|
-- FIFO module
|
-- FIFO module
|
-- 16K x 8B
|
-- 16K x 8B
|
component eb_wrapper
|
component FIFO_wrapper
|
port (
|
port (
|
wr_clk : IN std_logic;
|
wr_clk : IN std_logic;
|
wr_en : IN std_logic;
|
wr_en : IN std_logic;
|
din : IN std_logic_VECTOR(72-1 downto 0);
|
din : IN std_logic_VECTOR(72-1 downto 0);
|
pfull : OUT std_logic;
|
pfull : OUT std_logic;
|
| Line 312... |
Line 312... |
signal tab_sel : STD_LOGIC;
|
signal tab_sel : STD_LOGIC;
|
signal tab_we : STD_LOGIC_VECTOR (2-1 downto 0);
|
signal tab_we : STD_LOGIC_VECTOR (2-1 downto 0);
|
signal tab_wa : STD_LOGIC_VECTOR (12-1 downto 0);
|
signal tab_wa : STD_LOGIC_VECTOR (12-1 downto 0);
|
signal tab_wd : STD_LOGIC_VECTOR (C_DBUS_WIDTH-1 downto 0);
|
signal tab_wd : STD_LOGIC_VECTOR (C_DBUS_WIDTH-1 downto 0);
|
|
|
signal dg_running : STD_LOGIC;
|
-- signal dg_running : STD_LOGIC;
|
signal dg_mask : STD_LOGIC;
|
-- signal dg_mask : STD_LOGIC;
|
signal dg_rst : STD_LOGIC;
|
-- signal dg_rst : STD_LOGIC;
|
|
--
|
-- debug signal
|
-- -- debug signal
|
signal dg_debug_led : STD_LOGIC;
|
-- signal dg_debug_led : STD_LOGIC;
|
|
--
|
-- Protocol Interface module
|
-- -- Protocol Interface module
|
COMPONENT protocol_IF
|
-- COMPONENT protocol_IF
|
PORT (
|
-- PORT (
|
-- DAQ Tx
|
-- -- DAQ Tx
|
data2send_start : OUT std_logic;
|
-- data2send_start : OUT std_logic;
|
data2send_end : OUT std_logic;
|
-- data2send_end : OUT std_logic;
|
data2send : OUT std_logic_vector(64-1 downto 0);
|
-- data2send : OUT std_logic_vector(64-1 downto 0);
|
crc_error_send : OUT std_logic;
|
-- crc_error_send : OUT std_logic;
|
data2send_stop : IN std_logic;
|
-- data2send_stop : IN std_logic;
|
|
--
|
-- DAQ Rx
|
-- -- DAQ Rx
|
data_rec_start : IN std_logic;
|
-- data_rec_start : IN std_logic;
|
data_rec_end : IN std_logic;
|
-- data_rec_end : IN std_logic;
|
data_rec : IN std_logic_vector(64-1 downto 0);
|
-- data_rec : IN std_logic_vector(64-1 downto 0);
|
crc_error_rec : IN std_logic;
|
-- crc_error_rec : IN std_logic;
|
data_rec_stop : OUT std_logic;
|
-- data_rec_stop : OUT std_logic;
|
|
--
|
-- CTL Tx
|
-- -- CTL Tx
|
ctrl2send_start : OUT std_logic;
|
-- ctrl2send_start : OUT std_logic;
|
ctrl2send_end : OUT std_logic;
|
-- ctrl2send_end : OUT std_logic;
|
ctrl2send : OUT std_logic_vector(16-1 downto 0);
|
-- ctrl2send : OUT std_logic_vector(16-1 downto 0);
|
ctrl2send_stop : IN std_logic;
|
-- ctrl2send_stop : IN std_logic;
|
|
--
|
-- CTL Rx
|
-- -- CTL Rx
|
ctrl_rec_start : IN std_logic;
|
-- ctrl_rec_start : IN std_logic;
|
ctrl_rec_end : IN std_logic;
|
-- ctrl_rec_end : IN std_logic;
|
ctrl_rec : IN std_logic_vector(16-1 downto 0);
|
-- ctrl_rec : IN std_logic_vector(16-1 downto 0);
|
ctrl_rec_stop : OUT std_logic;
|
-- ctrl_rec_stop : OUT std_logic;
|
|
--
|
-- DLM Tx
|
-- -- DLM Tx
|
dlm2send_va : OUT std_logic;
|
-- dlm2send_va : OUT std_logic;
|
dlm2send_type : OUT std_logic_vector(4-1 downto 0);
|
-- dlm2send_type : OUT std_logic_vector(4-1 downto 0);
|
|
--
|
-- DLM Rx
|
-- -- DLM Rx
|
dlm_rec_va : IN std_logic;
|
-- dlm_rec_va : IN std_logic;
|
dlm_rec_type : IN std_logic_vector(4-1 downto 0);
|
-- dlm_rec_type : IN std_logic_vector(4-1 downto 0);
|
|
--
|
-- Common signals
|
-- -- Common signals
|
link_tx_clk : IN std_logic;
|
-- link_tx_clk : IN std_logic;
|
link_rx_clk : IN std_logic;
|
-- link_rx_clk : IN std_logic;
|
link_active : IN std_logic_vector(2-1 downto 0);
|
-- link_active : IN std_logic_vector(2-1 downto 0);
|
protocol_clk : OUT std_logic;
|
-- protocol_clk : OUT std_logic;
|
protocol_res_n : OUT std_logic;
|
-- protocol_res_n : OUT std_logic;
|
|
--
|
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
|
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
|
|
--
|
-- Fabric side: DAQ Rx
|
-- -- Fabric side: DAQ Rx
|
daq_rv : IN std_logic;
|
-- daq_rv : IN std_logic;
|
daq_rsof : IN std_logic;
|
-- daq_rsof : IN std_logic;
|
daq_reof : IN std_logic;
|
-- daq_reof : IN std_logic;
|
daq_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
-- daq_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
daq_rstop : OUT std_logic;
|
-- daq_rstop : OUT std_logic;
|
|
--
|
-- Fabric side: DAQ Tx
|
-- -- Fabric side: DAQ Tx
|
daq_tv : OUT std_logic;
|
-- daq_tv : OUT std_logic;
|
daq_tsof : OUT std_logic;
|
-- daq_tsof : OUT std_logic;
|
daq_teof : OUT std_logic;
|
-- daq_teof : OUT std_logic;
|
daq_td : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
-- daq_td : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
daq_tstop : IN std_logic;
|
-- daq_tstop : IN std_logic;
|
|
--
|
-- Fabric side: DLM Rx
|
-- -- Fabric side: DLM Rx
|
dlm_tv : IN std_logic;
|
-- dlm_tv : IN std_logic;
|
dlm_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- dlm_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
|
--
|
-- Fabric side: DLM Tx
|
-- -- Fabric side: DLM Tx
|
dlm_rv : OUT std_logic;
|
-- dlm_rv : OUT std_logic;
|
dlm_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- dlm_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
|
--
|
-- Fabric side: CTL Rx
|
-- -- Fabric side: CTL Rx
|
ctl_rv : IN std_logic;
|
-- ctl_rv : IN std_logic;
|
ctl_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- ctl_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
ctl_rstop : OUT std_logic;
|
-- ctl_rstop : OUT std_logic;
|
|
--
|
-- Fabric side: CTL Tx
|
-- -- Fabric side: CTL Tx
|
ctl_ttake : IN std_logic;
|
-- ctl_ttake : IN std_logic;
|
ctl_tv : OUT std_logic;
|
-- ctl_tv : OUT std_logic;
|
ctl_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- ctl_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
ctl_tstop : IN std_logic;
|
-- ctl_tstop : IN std_logic;
|
|
--
|
ctl_reset : IN std_logic;
|
-- ctl_reset : IN std_logic;
|
ctl_status : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- ctl_status : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
|
--
|
-- Interrupter triggers
|
-- -- Interrupter triggers
|
DAQ_irq : OUT std_logic;
|
-- DAQ_irq : OUT std_logic;
|
CTL_irq : OUT std_logic;
|
-- CTL_irq : OUT std_logic;
|
DLM_irq : OUT std_logic;
|
-- DLM_irq : OUT std_logic;
|
|
--
|
-- Data generator table write port
|
-- -- Data generator table write port
|
tab_sel : IN STD_LOGIC;
|
-- tab_sel : IN STD_LOGIC;
|
tab_we : IN STD_LOGIC_VECTOR (2-1 downto 0);
|
-- tab_we : IN STD_LOGIC_VECTOR (2-1 downto 0);
|
tab_wa : IN STD_LOGIC_VECTOR (12-1 downto 0);
|
-- tab_wa : IN STD_LOGIC_VECTOR (12-1 downto 0);
|
tab_wd : IN STD_LOGIC_VECTOR (64-1 downto 0);
|
-- tab_wd : IN STD_LOGIC_VECTOR (64-1 downto 0);
|
|
--
|
-- DG control/status signal
|
-- -- DG control/status signal
|
dg_running : OUT STD_LOGIC;
|
-- dg_running : OUT STD_LOGIC;
|
dg_mask : IN STD_LOGIC;
|
-- dg_mask : IN STD_LOGIC;
|
dg_rst : IN STD_LOGIC;
|
-- dg_rst : IN STD_LOGIC;
|
|
--
|
-- DG debug signal
|
-- -- DG debug signal
|
daq_start_led : OUT STD_LOGIC;
|
-- daq_start_led : OUT STD_LOGIC;
|
|
--
|
-- Fabric side: Common signals
|
-- -- Fabric side: Common signals
|
trn_clk : IN std_logic;
|
-- trn_clk : IN std_logic;
|
protocol_link_act : OUT std_logic_vector(2-1 downto 0);
|
-- protocol_link_act : OUT std_logic_vector(2-1 downto 0);
|
protocol_rst : IN std_logic
|
-- protocol_rst : IN std_logic
|
);
|
-- );
|
END COMPONENT;
|
-- END COMPONENT;
|
|
--
|
-- DAQ Tx
|
-- -- DAQ Tx
|
signal data2send_start : std_logic;
|
-- signal data2send_start : std_logic;
|
signal data2send_end : std_logic;
|
-- signal data2send_end : std_logic;
|
signal data2send : std_logic_vector(64-1 downto 0);
|
-- signal data2send : std_logic_vector(64-1 downto 0);
|
signal crc_error_send : std_logic;
|
-- signal crc_error_send : std_logic;
|
signal data2send_stop : std_logic
|
-- signal data2send_stop : std_logic
|
:= '0';
|
-- := '0';
|
|
--
|
-- DAQ Rx
|
-- -- DAQ Rx
|
signal data_rec_start : std_logic;
|
-- signal data_rec_start : std_logic;
|
signal data_rec_end : std_logic;
|
-- signal data_rec_end : std_logic;
|
signal data_rec : std_logic_vector(64-1 downto 0);
|
-- signal data_rec : std_logic_vector(64-1 downto 0);
|
signal crc_error_rec : std_logic;
|
-- signal crc_error_rec : std_logic;
|
signal data_rec_stop : std_logic;
|
-- signal data_rec_stop : std_logic;
|
|
--
|
-- CTL Tx
|
-- -- CTL Tx
|
signal ctrl2send_start : std_logic;
|
-- signal ctrl2send_start : std_logic;
|
signal ctrl2send_end : std_logic;
|
-- signal ctrl2send_end : std_logic;
|
signal ctrl2send : std_logic_vector(16-1 downto 0);
|
-- signal ctrl2send : std_logic_vector(16-1 downto 0);
|
signal ctrl2send_stop : std_logic;
|
-- signal ctrl2send_stop : std_logic;
|
|
--
|
-- CTL Rx
|
-- -- CTL Rx
|
signal ctrl_rec_start : std_logic;
|
-- signal ctrl_rec_start : std_logic;
|
signal ctrl_rec_end : std_logic;
|
-- signal ctrl_rec_end : std_logic;
|
signal ctrl_rec : std_logic_vector(16-1 downto 0);
|
-- signal ctrl_rec : std_logic_vector(16-1 downto 0);
|
signal ctrl_rec_stop : std_logic;
|
-- signal ctrl_rec_stop : std_logic;
|
|
--
|
-- DLM Tx
|
-- -- DLM Tx
|
signal dlm2send_va : std_logic;
|
-- signal dlm2send_va : std_logic;
|
signal dlm2send_type : std_logic_vector(4-1 downto 0);
|
-- signal dlm2send_type : std_logic_vector(4-1 downto 0);
|
-- signal dlm2send_va_i : std_logic;
|
---- signal dlm2send_va_i : std_logic;
|
-- signal dlm2send_type_i : std_logic_vector(4-1 downto 0);
|
---- signal dlm2send_type_i : std_logic_vector(4-1 downto 0);
|
|
--
|
-- DLM Rx
|
-- -- DLM Rx
|
signal dlm_rec_va : std_logic;
|
-- signal dlm_rec_va : std_logic;
|
signal dlm_rec_type : std_logic_vector(4-1 downto 0);
|
-- signal dlm_rec_type : std_logic_vector(4-1 downto 0);
|
-- signal dlm_rec_va_i : std_logic;
|
---- signal dlm_rec_va_i : std_logic;
|
-- signal dlm_rec_type_i : std_logic_vector(4-1 downto 0);
|
---- signal dlm_rec_type_i : std_logic_vector(4-1 downto 0);
|
|
--
|
|
--
|
-- Common signals
|
-- -- Common signals
|
signal link_rx_clk : std_logic;
|
-- signal link_rx_clk : std_logic;
|
signal link_tx_clk : std_logic;
|
-- signal link_tx_clk : std_logic;
|
signal link_active : std_logic_vector(2-1 downto 0);
|
-- signal link_active : std_logic_vector(2-1 downto 0);
|
signal protocol_clk : std_logic;
|
-- signal protocol_clk : std_logic;
|
signal protocol_res_n : std_logic;
|
-- signal protocol_res_n : std_logic;
|
|
--
|
|
--
|
-- Fabric side: DAQ Rx
|
-- -- Fabric side: DAQ Rx
|
signal daq_rv : std_logic;
|
-- signal daq_rv : std_logic;
|
signal daq_rsof : std_logic;
|
-- signal daq_rsof : std_logic;
|
signal daq_reof : std_logic;
|
-- signal daq_reof : std_logic;
|
signal daq_rd : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
-- signal daq_rd : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
signal daq_rstop : std_logic;
|
-- signal daq_rstop : std_logic;
|
|
--
|
-- Fabric side: DAQ Tx
|
-- -- Fabric side: DAQ Tx
|
signal daq_tv : std_logic;
|
-- signal daq_tv : std_logic;
|
signal daq_tsof : std_logic;
|
-- signal daq_tsof : std_logic;
|
signal daq_teof : std_logic;
|
-- signal daq_teof : std_logic;
|
signal daq_td : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
-- signal daq_td : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
signal daq_tstop : std_logic;
|
-- signal daq_tstop : std_logic;
|
|
--
|
-- Fabric side: DLM Rx
|
-- -- Fabric side: DLM Rx
|
signal dlm_tv : std_logic;
|
-- signal dlm_tv : std_logic;
|
signal dlm_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- signal dlm_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
|
--
|
-- Fabric side: DLM Tx
|
-- -- Fabric side: DLM Tx
|
signal dlm_rv : std_logic;
|
-- signal dlm_rv : std_logic;
|
signal dlm_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- signal dlm_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
|
--
|
-- Fabric side: CTL Rx
|
-- -- Fabric side: CTL Rx
|
signal ctl_rv : std_logic;
|
-- signal ctl_rv : std_logic;
|
signal ctl_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- signal ctl_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
signal ctl_rstop : std_logic;
|
-- signal ctl_rstop : std_logic;
|
|
--
|
-- Fabric side: CTL Tx
|
-- -- Fabric side: CTL Tx
|
signal ctl_ttake : std_logic;
|
-- signal ctl_ttake : std_logic;
|
signal ctl_tv : std_logic;
|
-- signal ctl_tv : std_logic;
|
signal ctl_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- signal ctl_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
signal ctl_tstop : std_logic;
|
-- signal ctl_tstop : std_logic;
|
|
--
|
signal ctl_reset : std_logic;
|
-- signal ctl_reset : std_logic;
|
signal ctl_status : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- signal ctl_status : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
|
--
|
-- Interrupter triggers
|
-- -- Interrupter triggers
|
signal DAQ_irq : std_logic;
|
-- signal DAQ_irq : std_logic;
|
signal CTL_irq : std_logic;
|
-- signal CTL_irq : std_logic;
|
signal DLM_irq : std_logic;
|
-- signal DLM_irq : std_logic;
|
|
--
|
-- Fabric side: Common signals
|
-- -- Fabric side: Common signals
|
signal protocol_link_act : std_logic_vector(2-1 downto 0);
|
-- signal protocol_link_act : std_logic_vector(2-1 downto 0);
|
signal protocol_rst : std_logic;
|
-- signal protocol_rst : std_logic;
|
|
--
|
|
--
|
-- Pseudo link module, to be replaced by the real optical link
|
-- -- Pseudo link module, to be replaced by the real optical link
|
COMPONENT pseudo_protocol_module
|
-- COMPONENT pseudo_protocol_module
|
PORT (
|
-- PORT (
|
-- DAQ Tx
|
-- -- DAQ Tx
|
data2send_start : IN std_logic;
|
-- data2send_start : IN std_logic;
|
data2send_end : IN std_logic;
|
-- data2send_end : IN std_logic;
|
data2send : IN std_logic_vector(64-1 downto 0);
|
-- data2send : IN std_logic_vector(64-1 downto 0);
|
crc_error_send : IN std_logic;
|
-- crc_error_send : IN std_logic;
|
data2send_stop : OUT std_logic;
|
-- data2send_stop : OUT std_logic;
|
|
--
|
-- DAQ Rx
|
-- -- DAQ Rx
|
data_rec_start : OUT std_logic;
|
-- data_rec_start : OUT std_logic;
|
data_rec_end : OUT std_logic;
|
-- data_rec_end : OUT std_logic;
|
data_rec : OUT std_logic_vector(64-1 downto 0);
|
-- data_rec : OUT std_logic_vector(64-1 downto 0);
|
crc_error_rec : OUT std_logic;
|
-- crc_error_rec : OUT std_logic;
|
data_rec_stop : IN std_logic;
|
-- data_rec_stop : IN std_logic;
|
|
--
|
-- CTL Tx
|
-- -- CTL Tx
|
ctrl2send_start : IN std_logic;
|
-- ctrl2send_start : IN std_logic;
|
ctrl2send_end : IN std_logic;
|
-- ctrl2send_end : IN std_logic;
|
ctrl2send : IN std_logic_vector(16-1 downto 0);
|
-- ctrl2send : IN std_logic_vector(16-1 downto 0);
|
ctrl2send_stop : OUT std_logic;
|
-- ctrl2send_stop : OUT std_logic;
|
|
--
|
-- CTL Rx
|
-- -- CTL Rx
|
ctrl_rec_start : OUT std_logic;
|
-- ctrl_rec_start : OUT std_logic;
|
ctrl_rec_end : OUT std_logic;
|
-- ctrl_rec_end : OUT std_logic;
|
ctrl_rec : OUT std_logic_vector(16-1 downto 0);
|
-- ctrl_rec : OUT std_logic_vector(16-1 downto 0);
|
ctrl_rec_stop : IN std_logic;
|
-- ctrl_rec_stop : IN std_logic;
|
|
--
|
-- DLM Tx
|
-- -- DLM Tx
|
dlm2send_va : IN std_logic;
|
-- dlm2send_va : IN std_logic;
|
dlm2send_type : IN std_logic_vector(4-1 downto 0);
|
-- dlm2send_type : IN std_logic_vector(4-1 downto 0);
|
|
--
|
-- DLM Rx
|
-- -- DLM Rx
|
dlm_rec_va : OUT std_logic;
|
-- dlm_rec_va : OUT std_logic;
|
dlm_rec_type : OUT std_logic_vector(4-1 downto 0);
|
-- dlm_rec_type : OUT std_logic_vector(4-1 downto 0);
|
|
--
|
-- dummy pin input
|
-- -- dummy pin input
|
dummy_pin_in : IN std_logic_vector(3-1 downto 0);
|
-- dummy_pin_in : IN std_logic_vector(3-1 downto 0);
|
|
--
|
-- Common interface
|
-- -- Common interface
|
link_tx_clk : OUT std_logic;
|
-- link_tx_clk : OUT std_logic;
|
link_rx_clk : OUT std_logic;
|
-- link_rx_clk : OUT std_logic;
|
link_active : OUT std_logic_vector(2-1 downto 0);
|
-- link_active : OUT std_logic_vector(2-1 downto 0);
|
clk : IN std_logic;
|
-- clk : IN std_logic;
|
res_n : IN std_logic
|
-- res_n : IN std_logic
|
);
|
-- );
|
END COMPONENT;
|
-- END COMPONENT;
|
|
--
|
|
--
|
signal Link_Buf_full : std_logic;
|
-- signal Link_Buf_full : std_logic;
|
|
|
|
|
------------- COMPONENT Declaration: tlpControl ------
|
------------- COMPONENT Declaration: tlpControl ------
|
--
|
--
|
component tlpControl
|
component tlpControl
|
port (
|
port (
|
-- Test pin, emulating DDR data flow discontinuity
|
-- Test pin, emulating DDR data flow discontinuity
|
mbuf_UserFull : IN std_logic;
|
mbuf_UserFull : IN std_logic;
|
trn_Blinker : OUT std_logic;
|
trn_Blinker : OUT std_logic;
|
|
|
-- DCB protocol interface
|
-- -- DCB protocol interface
|
protocol_link_act : IN std_logic_vector(2-1 downto 0);
|
-- protocol_link_act : IN std_logic_vector(2-1 downto 0);
|
protocol_rst : OUT std_logic;
|
-- protocol_rst : OUT std_logic;
|
|
--
|
-- Interrupter triggers
|
-- -- Interrupter triggers
|
DAQ_irq : IN std_logic;
|
-- DAQ_irq : IN std_logic;
|
CTL_irq : IN std_logic;
|
-- CTL_irq : IN std_logic;
|
DLM_irq : IN std_logic;
|
-- DLM_irq : IN std_logic;
|
|
--
|
-- Fabric side: CTL Rx
|
-- -- Fabric side: CTL Rx
|
ctl_rv : OUT std_logic;
|
-- ctl_rv : OUT std_logic;
|
ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
|
--
|
-- Fabric side: CTL Tx
|
-- -- Fabric side: CTL Tx
|
ctl_ttake : OUT std_logic;
|
-- ctl_ttake : OUT std_logic;
|
ctl_tv : IN std_logic;
|
-- ctl_tv : IN std_logic;
|
ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
ctl_tstop : OUT std_logic;
|
-- ctl_tstop : OUT std_logic;
|
|
--
|
ctl_reset : OUT std_logic;
|
-- ctl_reset : OUT std_logic;
|
ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
|
--
|
-- Fabric side: DLM Rx
|
-- -- Fabric side: DLM Rx
|
dlm_tv : OUT std_logic;
|
-- dlm_tv : OUT std_logic;
|
dlm_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- dlm_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
|
--
|
-- Fabric side: DLM Tx
|
-- -- Fabric side: DLM Tx
|
dlm_rv : IN std_logic;
|
-- dlm_rv : IN std_logic;
|
dlm_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- dlm_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
|
--
|
Link_Buf_full : IN std_logic;
|
-- Link_Buf_full : IN std_logic;
|
|
|
-- Event Buffer FIFO interface
|
-- Event Buffer FIFO interface
|
eb_FIFO_we : OUT std_logic;
|
eb_FIFO_we : OUT std_logic;
|
eb_FIFO_wsof : OUT std_logic;
|
eb_FIFO_wsof : OUT std_logic;
|
eb_FIFO_weof : OUT std_logic;
|
eb_FIFO_weof : OUT std_logic;
|
| Line 672... |
Line 672... |
-- DDR payload FIFO Read Port
|
-- DDR payload FIFO Read Port
|
DDR_FIFO_RdEn : OUT std_logic;
|
DDR_FIFO_RdEn : OUT std_logic;
|
DDR_FIFO_Empty : IN std_logic;
|
DDR_FIFO_Empty : IN std_logic;
|
DDR_FIFO_RdQout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
DDR_FIFO_RdQout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
|
|
-- Data generator table write
|
-- -- Data generator table write
|
tab_we : OUT std_logic_vector(2-1 downto 0);
|
-- tab_we : OUT std_logic_vector(2-1 downto 0);
|
tab_wa : OUT std_logic_vector(12-1 downto 0);
|
-- tab_wa : OUT std_logic_vector(12-1 downto 0);
|
tab_wd : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
-- tab_wd : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
|
--
|
-- Data generator control
|
-- -- Data generator control
|
DG_is_Running : IN std_logic;
|
-- DG_is_Running : IN std_logic;
|
DG_Reset : OUT std_logic;
|
-- DG_Reset : OUT std_logic;
|
DG_Mask : OUT std_logic;
|
-- DG_Mask : OUT std_logic;
|
|
|
-- Transaction layer interface
|
-- Transaction layer interface
|
trn_lnk_up_n : IN std_logic;
|
trn_lnk_up_n : IN std_logic;
|
trn_rsrc_dsc_n : IN std_logic;
|
trn_rsrc_dsc_n : IN std_logic;
|
trn_rnp_ok_n : OUT std_logic;
|
trn_rnp_ok_n : OUT std_logic;
|
| Line 1047... |
Line 1047... |
-- trn_td (63 downto 32) <= not trn_td (31 downto 0);
|
-- trn_td (63 downto 32) <= not trn_td (31 downto 0);
|
|
|
end generate;
|
end generate;
|
|
|
|
|
|
-- DAQ_irq <= eb_empty;
|
DAQ_irq <= eb_empty;
|
|
|
|
|
|
-- ---------------------------------------------------------------
|
-- ---------------------------------------------------------------
|
-- tlp control module
|
-- tlp control module
|
--
|
--
|
| Line 1061... |
Line 1060... |
port map (
|
port map (
|
|
|
mbuf_UserFull => '0' ,
|
mbuf_UserFull => '0' ,
|
trn_Blinker => trn_Blinker ,
|
trn_Blinker => trn_Blinker ,
|
|
|
-- DCB protocol interface
|
-- -- DCB protocol interface
|
protocol_link_act => protocol_link_act , -- IN std_logic_vector(2-1 downto 0);
|
-- protocol_link_act => protocol_link_act , -- IN std_logic_vector(2-1 downto 0);
|
protocol_rst => protocol_rst , -- OUT std_logic;
|
-- protocol_rst => protocol_rst , -- OUT std_logic;
|
|
--
|
Link_Buf_Full => daq_rstop , -- IN std_logic;
|
-- Link_Buf_Full => daq_rstop , -- IN std_logic;
|
|
--
|
-- Interrupter triggers
|
-- -- Interrupter triggers
|
DAQ_irq => DAQ_irq , -- IN std_logic;
|
-- DAQ_irq => DAQ_irq , -- IN std_logic;
|
CTL_irq => CTL_irq , -- IN std_logic;
|
-- CTL_irq => CTL_irq , -- IN std_logic;
|
DLM_irq => DLM_irq , -- IN std_logic;
|
-- DLM_irq => DLM_irq , -- IN std_logic;
|
|
--
|
-- Fabric side: CTL Rx
|
-- -- Fabric side: CTL Rx
|
ctl_rv => ctl_rv , -- OUT std_logic;
|
-- ctl_rv => ctl_rv , -- OUT std_logic;
|
ctl_rd => ctl_rd , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- ctl_rd => ctl_rd , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
|
--
|
-- Fabric side: CTL Tx
|
-- -- Fabric side: CTL Tx
|
ctl_ttake => ctl_ttake , -- OUT std_logic;
|
-- ctl_ttake => ctl_ttake , -- OUT std_logic;
|
ctl_tv => ctl_tv , -- IN std_logic;
|
-- ctl_tv => ctl_tv , -- IN std_logic;
|
ctl_td => ctl_td , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- ctl_td => ctl_td , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
ctl_tstop => ctl_tstop , -- OUT std_logic;
|
-- ctl_tstop => ctl_tstop , -- OUT std_logic;
|
|
--
|
ctl_reset => ctl_reset , -- OUT std_logic;
|
-- ctl_reset => ctl_reset , -- OUT std_logic;
|
ctl_status => ctl_status , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- ctl_status => ctl_status , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
|
--
|
-- Fabric side: DLM Rx
|
-- -- Fabric side: DLM Rx
|
dlm_tv => dlm_tv , -- OUT std_logic;
|
-- dlm_tv => dlm_tv , -- OUT std_logic;
|
dlm_td => dlm_td , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- dlm_td => dlm_td , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
|
--
|
-- Fabric side: DLM Tx
|
-- -- Fabric side: DLM Tx
|
dlm_rv => dlm_rv , -- IN std_logic;
|
-- dlm_rv => dlm_rv , -- IN std_logic;
|
dlm_rd => dlm_rd , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
-- dlm_rd => dlm_rd , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
|
|
|
-- Event Buffer FIFO interface
|
-- Event Buffer FIFO interface
|
eb_FIFO_we => eb_we , -- OUT std_logic;
|
eb_FIFO_we => eb_we , -- OUT std_logic;
|
eb_FIFO_wsof => eb_wsof , -- OUT std_logic;
|
eb_FIFO_wsof => eb_wsof , -- OUT std_logic;
|
eb_FIFO_weof => eb_weof , -- OUT std_logic;
|
eb_FIFO_weof => eb_weof , -- OUT std_logic;
|
| Line 1154... |
Line 1153... |
-- DDR payload FIFO Read Port
|
-- DDR payload FIFO Read Port
|
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- OUT std_logic;
|
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- OUT std_logic;
|
DDR_FIFO_Empty => DDR_FIFO_Empty , -- IN std_logic;
|
DDR_FIFO_Empty => DDR_FIFO_Empty , -- IN std_logic;
|
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
|
|
-- Data generator table write
|
-- -- Data generator table write
|
tab_we => tab_we , -- OUT std_logic_vector(2-1 downto 0);
|
-- tab_we => tab_we , -- OUT std_logic_vector(2-1 downto 0);
|
tab_wa => tab_wa , -- OUT std_logic_vector(12-1 downto 0);
|
-- tab_wa => tab_wa , -- OUT std_logic_vector(12-1 downto 0);
|
tab_wd => tab_wd , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
-- tab_wd => tab_wd , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
|
|
DG_is_Running => dg_running , -- IN std_logic;
|
-- DG_is_Running => dg_running , -- IN std_logic;
|
DG_Reset => dg_rst , -- OUT STD_LOGIC;
|
-- DG_Reset => dg_rst , -- OUT STD_LOGIC;
|
DG_Mask => dg_mask , -- OUT STD_LOGIC
|
-- DG_Mask => dg_mask , -- OUT STD_LOGIC
|
|
|
-------------------
|
-------------------
|
-- Transaction Interface
|
-- Transaction Interface
|
trn_lnk_up_n => trn_lnk_up_n,
|
trn_lnk_up_n => trn_lnk_up_n,
|
trn_rsrc_dsc_n => trn_rsrc_dsc_n,
|
trn_rsrc_dsc_n => trn_rsrc_dsc_n,
|
| Line 1261... |
Line 1260... |
|
|
--
|
--
|
-- Event Buffer wrapper
|
-- Event Buffer wrapper
|
--
|
--
|
|
|
LEDs_IO_pin(0) <= trn_reset_n xor Format_Shower;
|
LEDs_IO_pin(0) <= trn_reset_n;
|
LEDs_IO_pin(1) <= trn_lnk_up_n xor DDR_Blinker;
|
LEDs_IO_pin(1) <= trn_lnk_up_n;
|
LEDs_IO_pin(2) <= link_active(0);
|
LEDs_IO_pin(2) <= Format_Shower;
|
LEDs_IO_pin(3) <= link_active(1); -- dg_debug_led;
|
LEDs_IO_pin(3) <= DDR_Blinker;
|
|
|
|
|
event_buffer0:
|
queue_buffer:
|
eb_wrapper
|
FIFO_wrapper
|
port map (
|
port map (
|
wr_clk => trn_clk , -- eb_wclk ,
|
wr_clk => trn_clk , -- eb_wclk ,
|
wr_en => eb_we_up ,
|
wr_en => eb_we ,
|
din => eb_din_up ,
|
din => eb_din ,
|
pfull => eb_pfull ,
|
pfull => eb_pfull ,
|
full => eb_full ,
|
full => eb_full ,
|
|
|
rd_clk => trn_clk , -- eb_rclk ,
|
rd_clk => trn_clk , -- eb_rclk ,
|
rd_en => eb_re ,
|
rd_en => eb_re ,
|
| Line 1302... |
Line 1301... |
eb_FIFO_Status(C_FIFO_DC_WIDTH+2 downto 3)
|
eb_FIFO_Status(C_FIFO_DC_WIDTH+2 downto 3)
|
<= eb_data_count(C_FIFO_DC_WIDTH downto 1);
|
<= eb_data_count(C_FIFO_DC_WIDTH downto 1);
|
eb_FIFO_Status(2) <= eb_full; -- daq_rstop;
|
eb_FIFO_Status(2) <= eb_full; -- daq_rstop;
|
eb_FIFO_Status(1) <= eb_pfull;
|
eb_FIFO_Status(1) <= eb_pfull;
|
eb_FIFO_Status(0) <= eb_empty;
|
eb_FIFO_Status(0) <= eb_empty;
|
eb_FIFO_ow <= eb_we_up and eb_full;
|
eb_FIFO_ow <= eb_we and eb_full;
|
|
|
|
|
|
-- --
|
|
-- -- .......................
|
|
-- --
|
--
|
--
|
-- .......................
|
-- daq_rv <= eb_we;
|
|
-- daq_rsof <= eb_wsof;
|
|
-- daq_reof <= eb_weof;
|
|
-- daq_rd <= eb_din(C_DBUS_WIDTH-1 downto 0);
|
--
|
--
|
|
-- eb_we_up <= daq_tv or self_feed_daq;
|
daq_rv <= eb_we;
|
-- eb_din_up <= C_ALL_ZEROS(72-1 downto C_DBUS_WIDTH+2) & daq_tsof & daq_teof & daq_td;
|
daq_rsof <= eb_wsof;
|
-- daq_tstop <= eb_pfull;
|
daq_reof <= eb_weof;
|
|
daq_rd <= eb_din(C_DBUS_WIDTH-1 downto 0);
|
|
|
|
eb_we_up <= daq_tv or self_feed_daq;
|
|
eb_din_up <= C_ALL_ZEROS(72-1 downto C_DBUS_WIDTH+2) & daq_tsof & daq_teof & daq_td;
|
|
daq_tstop <= eb_pfull;
|
|
|
|
|
|
--
|
--
|
-- Protocol Interface
|
|
--
|
--
|
ABB_DCB_Interface0:
|
-- --
|
protocol_IF
|
-- -- Protocol Interface
|
port map (
|
-- --
|
-- DAQ Tx
|
-- ABB_DCB_Interface0:
|
data2send_start => data2send_start , -- OUT std_logic;
|
-- protocol_IF
|
data2send_end => data2send_end , -- OUT std_logic;
|
-- port map (
|
data2send => data2send , -- OUT std_logic_vector(16-1 downto 0);
|
-- -- DAQ Tx
|
crc_error_send => crc_error_send , -- OUT std_logic;
|
-- data2send_start => data2send_start , -- OUT std_logic;
|
data2send_stop => data2send_stop , -- IN std_logic;
|
-- data2send_end => data2send_end , -- OUT std_logic;
|
|
-- data2send => data2send , -- OUT std_logic_vector(16-1 downto 0);
|
-- DAQ Rx
|
-- crc_error_send => crc_error_send , -- OUT std_logic;
|
data_rec_start => data_rec_start , -- IN std_logic;
|
-- data2send_stop => data2send_stop , -- IN std_logic;
|
data_rec_end => data_rec_end , -- IN std_logic;
|
--
|
data_rec => data_rec , -- IN std_logic_vector(16-1 downto 0);
|
-- -- DAQ Rx
|
crc_error_rec => crc_error_rec , -- IN std_logic;
|
-- data_rec_start => data_rec_start , -- IN std_logic;
|
data_rec_stop => data_rec_stop , -- OUT std_logic;
|
-- data_rec_end => data_rec_end , -- IN std_logic;
|
|
-- data_rec => data_rec , -- IN std_logic_vector(16-1 downto 0);
|
-- CTL Tx
|
-- crc_error_rec => crc_error_rec , -- IN std_logic;
|
ctrl2send_start => ctrl2send_start , -- OUT std_logic;
|
-- data_rec_stop => data_rec_stop , -- OUT std_logic;
|
ctrl2send_end => ctrl2send_end , -- OUT std_logic;
|
--
|
ctrl2send => ctrl2send , -- OUT std_logic_vector(16-1 downto 0);
|
-- -- CTL Tx
|
ctrl2send_stop => ctrl2send_stop , -- IN std_logic;
|
-- ctrl2send_start => ctrl2send_start , -- OUT std_logic;
|
|
-- ctrl2send_end => ctrl2send_end , -- OUT std_logic;
|
-- CTL Rx
|
-- ctrl2send => ctrl2send , -- OUT std_logic_vector(16-1 downto 0);
|
ctrl_rec_start => ctrl_rec_start , -- IN std_logic;
|
-- ctrl2send_stop => ctrl2send_stop , -- IN std_logic;
|
ctrl_rec_end => ctrl_rec_end , -- IN std_logic;
|
--
|
ctrl_rec => ctrl_rec , -- IN std_logic_vector(16-1 downto 0);
|
-- -- CTL Rx
|
ctrl_rec_stop => ctrl_rec_stop , -- OUT std_logic;
|
-- ctrl_rec_start => ctrl_rec_start , -- IN std_logic;
|
|
-- ctrl_rec_end => ctrl_rec_end , -- IN std_logic;
|
-- DLM Tx
|
-- ctrl_rec => ctrl_rec , -- IN std_logic_vector(16-1 downto 0);
|
dlm2send_va => dlm2send_va , -- OUT std_logic;
|
-- ctrl_rec_stop => ctrl_rec_stop , -- OUT std_logic;
|
dlm2send_type => dlm2send_type , -- OUT std_logic_vector(4-1 downto 0);
|
--
|
|
-- -- DLM Tx
|
-- DLM Rx
|
-- dlm2send_va => dlm2send_va , -- OUT std_logic;
|
dlm_rec_va => dlm_rec_va , -- IN std_logic;
|
-- dlm2send_type => dlm2send_type , -- OUT std_logic_vector(4-1 downto 0);
|
dlm_rec_type => dlm_rec_type , -- IN std_logic_vector(4-1 downto 0);
|
--
|
|
-- -- DLM Rx
|
-- Common signals
|
-- dlm_rec_va => dlm_rec_va , -- IN std_logic;
|
link_tx_clk => link_tx_clk , -- IN std_logic;
|
-- dlm_rec_type => dlm_rec_type , -- IN std_logic_vector(4-1 downto 0);
|
link_rx_clk => link_rx_clk , -- IN std_logic;
|
--
|
link_active => link_active , -- IN std_logic_vector(2-1 downto 0);
|
-- -- Common signals
|
protocol_clk => protocol_clk , -- OUT std_logic;
|
-- link_tx_clk => link_tx_clk , -- IN std_logic;
|
protocol_res_n => protocol_res_n , -- OUT std_logic;
|
-- link_rx_clk => link_rx_clk , -- IN std_logic;
|
|
-- link_active => link_active , -- IN std_logic_vector(2-1 downto 0);
|
|
-- protocol_clk => protocol_clk , -- OUT std_logic;
|
-- Fabric side: DAQ Rx
|
-- protocol_res_n => protocol_res_n , -- OUT std_logic;
|
daq_rv => daq_rv , -- IN std_logic;
|
--
|
daq_rsof => daq_rsof , -- IN std_logic;
|
--
|
daq_reof => daq_reof , -- IN std_logic;
|
-- -- Fabric side: DAQ Rx
|
daq_rd => daq_rd , -- IN std_logic_vector(64-1 downto 0);
|
-- daq_rv => daq_rv , -- IN std_logic;
|
daq_rstop => daq_rstop , -- OUT std_logic;
|
-- daq_rsof => daq_rsof , -- IN std_logic;
|
|
-- daq_reof => daq_reof , -- IN std_logic;
|
-- Fabric side: DAQ Tx
|
-- daq_rd => daq_rd , -- IN std_logic_vector(64-1 downto 0);
|
daq_tv => daq_tv , -- OUT std_logic;
|
-- daq_rstop => daq_rstop , -- OUT std_logic;
|
daq_tsof => daq_tsof , -- OUT std_logic;
|
--
|
daq_teof => daq_teof , -- OUT std_logic;
|
-- -- Fabric side: DAQ Tx
|
daq_td => daq_td , -- OUT std_logic_vector(64-1 downto 0);
|
-- daq_tv => daq_tv , -- OUT std_logic;
|
daq_tstop => daq_tstop , -- IN std_logic;
|
-- daq_tsof => daq_tsof , -- OUT std_logic;
|
|
-- daq_teof => daq_teof , -- OUT std_logic;
|
-- Fabric side: CTL Rx
|
-- daq_td => daq_td , -- OUT std_logic_vector(64-1 downto 0);
|
ctl_rv => ctl_rv , -- IN std_logic;
|
-- daq_tstop => daq_tstop , -- IN std_logic;
|
ctl_rd => ctl_rd , -- IN std_logic_vector(32-1 downto 0);
|
--
|
ctl_rstop => ctl_rstop , -- OUT std_logic;
|
-- -- Fabric side: CTL Rx
|
|
-- ctl_rv => ctl_rv , -- IN std_logic;
|
-- Fabric side: CTL Tx
|
-- ctl_rd => ctl_rd , -- IN std_logic_vector(32-1 downto 0);
|
ctl_ttake => ctl_ttake , -- IN std_logic;
|
-- ctl_rstop => ctl_rstop , -- OUT std_logic;
|
ctl_tv => ctl_tv , -- OUT std_logic;
|
--
|
ctl_td => ctl_td , -- OUT std_logic_vector(32-1 downto 0);
|
-- -- Fabric side: CTL Tx
|
ctl_tstop => ctl_tstop , -- IN std_logic;
|
-- ctl_ttake => ctl_ttake , -- IN std_logic;
|
|
-- ctl_tv => ctl_tv , -- OUT std_logic;
|
ctl_reset => ctl_reset , -- IN std_logic;
|
-- ctl_td => ctl_td , -- OUT std_logic_vector(32-1 downto 0);
|
ctl_status => ctl_status , -- OUT std_logic_vector(32-1 downto 0);
|
-- ctl_tstop => ctl_tstop , -- IN std_logic;
|
|
--
|
-- Fabric side: DLM Rx
|
-- ctl_reset => ctl_reset , -- IN std_logic;
|
dlm_tv => dlm_tv , -- IN std_logic;
|
-- ctl_status => ctl_status , -- OUT std_logic_vector(32-1 downto 0);
|
dlm_td => dlm_td , -- IN std_logic_vector(4-1 downto 0);
|
--
|
|
-- -- Fabric side: DLM Rx
|
-- Fabric side: DLM Tx
|
-- dlm_tv => dlm_tv , -- IN std_logic;
|
dlm_rv => dlm_rv , -- OUT std_logic;
|
-- dlm_td => dlm_td , -- IN std_logic_vector(4-1 downto 0);
|
dlm_rd => dlm_rd , -- OUT std_logic_vector(4-1 downto 0);
|
--
|
|
-- -- Fabric side: DLM Tx
|
-- Interrupter triggers
|
-- dlm_rv => dlm_rv , -- OUT std_logic;
|
DAQ_irq => open, -- DAQ_irq , -- OUT std_logic;
|
-- dlm_rd => dlm_rd , -- OUT std_logic_vector(4-1 downto 0);
|
CTL_irq => CTL_irq , -- OUT std_logic;
|
--
|
DLM_irq => DLM_irq , -- OUT std_logic;
|
-- -- Interrupter triggers
|
|
-- DAQ_irq => open, -- DAQ_irq , -- OUT std_logic;
|
-- Data generator table write port
|
-- CTL_irq => CTL_irq , -- OUT std_logic;
|
tab_sel => '1' , -- IN STD_LOGIC;
|
-- DLM_irq => DLM_irq , -- OUT std_logic;
|
tab_we => tab_we , -- IN STD_LOGIC_VECTOR (2-1 downto 0);
|
--
|
tab_wa => tab_wa , -- IN STD_LOGIC_VECTOR (12-1 downto 0);
|
-- -- Data generator table write port
|
tab_wd => tab_wd , -- IN STD_LOGIC_VECTOR (64-1 downto 0);
|
-- tab_sel => '1' , -- IN STD_LOGIC;
|
|
-- tab_we => tab_we , -- IN STD_LOGIC_VECTOR (2-1 downto 0);
|
-- DG control/status signal
|
-- tab_wa => tab_wa , -- IN STD_LOGIC_VECTOR (12-1 downto 0);
|
dg_running => dg_running , -- OUT STD_LOGIC;
|
-- tab_wd => tab_wd , -- IN STD_LOGIC_VECTOR (64-1 downto 0);
|
dg_mask => dg_mask , -- IN STD_LOGIC;
|
--
|
dg_rst => dg_rst , -- IN STD_LOGIC
|
-- -- DG control/status signal
|
|
-- dg_running => dg_running , -- OUT STD_LOGIC;
|
-- DG debug signal
|
-- dg_mask => dg_mask , -- IN STD_LOGIC;
|
daq_start_led => dg_debug_led , -- OUT STD_LOGIC;
|
-- dg_rst => dg_rst , -- IN STD_LOGIC
|
|
--
|
-- Fabric side: Common signals
|
-- -- DG debug signal
|
trn_clk => trn_clk , -- IN std_logic;
|
-- daq_start_led => dg_debug_led , -- OUT STD_LOGIC;
|
protocol_link_act => protocol_link_act , -- OUT std_logic_vector(2-1 downto 0);
|
--
|
protocol_rst => protocol_rst -- IN std_logic
|
-- -- Fabric side: Common signals
|
);
|
-- trn_clk => trn_clk , -- IN std_logic;
|
|
-- protocol_link_act => protocol_link_act , -- OUT std_logic_vector(2-1 downto 0);
|
|
-- protocol_rst => protocol_rst -- IN std_logic
|
|
-- );
|
--
|
--
|
-- Module emulating the link
|
|
--
|
--
|
|
-- --
|
DCB_Link_module0:
|
-- -- Module emulating the link
|
pseudo_protocol_module
|
-- --
|
port map (
|
--
|
-- DAQ Tx
|
-- DCB_Link_module0:
|
data2send_start => data2send_start , -- IN std_logic;
|
-- pseudo_protocol_module
|
data2send_end => data2send_end , -- IN std_logic;
|
-- port map (
|
data2send => data2send , -- IN std_logic_vector(16-1 downto 0);
|
-- -- DAQ Tx
|
crc_error_send => crc_error_send , -- IN std_logic;
|
-- data2send_start => data2send_start , -- IN std_logic;
|
data2send_stop => data2send_stop , -- OUT std_logic;
|
-- data2send_end => data2send_end , -- IN std_logic;
|
|
-- data2send => data2send , -- IN std_logic_vector(16-1 downto 0);
|
-- DAQ Rx
|
-- crc_error_send => crc_error_send , -- IN std_logic;
|
data_rec_start => data_rec_start , -- OUT std_logic;
|
-- data2send_stop => data2send_stop , -- OUT std_logic;
|
data_rec_end => data_rec_end , -- OUT std_logic;
|
--
|
data_rec => data_rec , -- OUT std_logic_vector(16-1 downto 0);
|
-- -- DAQ Rx
|
crc_error_rec => crc_error_rec , -- OUT std_logic;
|
-- data_rec_start => data_rec_start , -- OUT std_logic;
|
data_rec_stop => data_rec_stop , -- IN std_logic;
|
-- data_rec_end => data_rec_end , -- OUT std_logic;
|
|
-- data_rec => data_rec , -- OUT std_logic_vector(16-1 downto 0);
|
-- CTL Tx
|
-- crc_error_rec => crc_error_rec , -- OUT std_logic;
|
ctrl2send_start => ctrl2send_start , -- IN std_logic;
|
-- data_rec_stop => data_rec_stop , -- IN std_logic;
|
ctrl2send_end => ctrl2send_end , -- IN std_logic;
|
--
|
ctrl2send => ctrl2send , -- IN std_logic_vector(16-1 downto 0);
|
-- -- CTL Tx
|
ctrl2send_stop => ctrl2send_stop , -- OUT std_logic;
|
-- ctrl2send_start => ctrl2send_start , -- IN std_logic;
|
|
-- ctrl2send_end => ctrl2send_end , -- IN std_logic;
|
-- CTL Rx
|
-- ctrl2send => ctrl2send , -- IN std_logic_vector(16-1 downto 0);
|
ctrl_rec_start => ctrl_rec_start , -- OUT std_logic;
|
-- ctrl2send_stop => ctrl2send_stop , -- OUT std_logic;
|
ctrl_rec_end => ctrl_rec_end , -- OUT std_logic;
|
--
|
ctrl_rec => ctrl_rec , -- OUT std_logic_vector(16-1 downto 0);
|
-- -- CTL Rx
|
ctrl_rec_stop => ctrl_rec_stop , -- IN std_logic;
|
-- ctrl_rec_start => ctrl_rec_start , -- OUT std_logic;
|
|
-- ctrl_rec_end => ctrl_rec_end , -- OUT std_logic;
|
-- DLM Tx
|
-- ctrl_rec => ctrl_rec , -- OUT std_logic_vector(16-1 downto 0);
|
dlm2send_va => dlm2send_va , -- IN std_logic;
|
-- ctrl_rec_stop => ctrl_rec_stop , -- IN std_logic;
|
dlm2send_type => dlm2send_type , -- IN std_logic_vector(4-1 downto 0);
|
--
|
|
-- -- DLM Tx
|
-- DLM Rx
|
-- dlm2send_va => dlm2send_va , -- IN std_logic;
|
dlm_rec_va => dlm_rec_va , -- OUT std_logic;
|
-- dlm2send_type => dlm2send_type , -- IN std_logic_vector(4-1 downto 0);
|
dlm_rec_type => dlm_rec_type , -- OUT std_logic_vector(4-1 downto 0);
|
--
|
|
-- -- DLM Rx
|
-- dummy pin input !!!! not really exists
|
-- dlm_rec_va => dlm_rec_va , -- OUT std_logic;
|
dummy_pin_in => "000", -- dummy_pin_in , -- IN std_logic_vector(3-1 downto 0);
|
-- dlm_rec_type => dlm_rec_type , -- OUT std_logic_vector(4-1 downto 0);
|
-- dummy_pin_in => dummy_pin_in , -- IN std_logic_vector(3-1 downto 0);
|
--
|
|
-- -- dummy pin input !!!! not really exists
|
-- Common interface
|
-- dummy_pin_in => "000", -- dummy_pin_in , -- IN std_logic_vector(3-1 downto 0);
|
link_tx_clk => link_tx_clk , -- OUT std_logic;
|
---- dummy_pin_in => dummy_pin_in , -- IN std_logic_vector(3-1 downto 0);
|
link_rx_clk => link_rx_clk , -- OUT std_logic;
|
--
|
link_active => link_active , -- OUT std_logic_vector(2-1 downto 0);
|
-- -- Common interface
|
clk => protocol_clk , -- IN std_logic;
|
-- link_tx_clk => link_tx_clk , -- OUT std_logic;
|
res_n => protocol_res_n -- IN std_logic
|
-- link_rx_clk => link_rx_clk , -- OUT std_logic;
|
);
|
-- link_active => link_active , -- OUT std_logic_vector(2-1 downto 0);
|
|
-- clk => protocol_clk , -- IN std_logic;
|
|
-- res_n => protocol_res_n -- IN std_logic
|
|
-- );
|
|
|
|
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
No newline at end of file
|
No newline at end of file
|
