| Line 34... |
Line 34... |
`define T_HALF_CYCLE_MEMCLK 5.0
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`define T_HALF_CYCLE_MEMCLK 5.0
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`define T_DELAY_AFTER 0.0
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`define T_DELAY_AFTER 0.0
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`define T_DELTA 0.1
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`define T_DELTA 0.1
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`define T_PIO_INTERVAL 50.0
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`define T_PIO_INTERVAL 50.0
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`define T_DMA_INTERVAL 300.0
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`define T_DMA_INTERVAL 300.0
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//`define T_DMA_TURN_AROUND 100.0
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//`define T_STATISTIC_INTERVAL 10000.0
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`define T_RX_NO_FC_PERIOD 1900000.0
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`define T_RX_NO_FC_PERIOD 1900000.0
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`define T_TX_NO_FC_PERIOD 1500000.0
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`define T_TX_NO_FC_PERIOD 1500000.0
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/* Memory size for simulation */
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/* Memory size for simulation */
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`define C_ARRAY_DIMENSION 4096
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`define C_ARRAY_DIMENSION 4096
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| Line 386... |
Line 384... |
mbuf_UserFull = 0;
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mbuf_UserFull = 0;
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pcie_link_width = 'H19;
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pcie_link_width = 'H19;
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cfg_dcommand = 'H2000;
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cfg_dcommand = 'H2000;
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localID = 'HD841;
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localID = 'HD841;
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Rx_No_Flow_Control = 0;
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Rx_No_Flow_Control = 1; // = 0; // Set to 0 to enable the Rx throttling
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Tx_No_Flow_Control = 0;
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Tx_No_Flow_Control = 1; // = 0; // Set to 0 to enable the Tx throttling
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// Wait some nanoseconds for global reset to finish
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// Wait some nanoseconds for global reset to finish
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#100;
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#100;
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trn_reset_n = 1;
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trn_reset_n = 1;
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trn_lnk_up_n = 0;
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trn_lnk_up_n = 0;
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| Line 461... |
Line 459... |
Gap_Insert_Rx;
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Gap_Insert_Rx;
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PIO_bar <= -1;
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PIO_bar <= -1;
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DMA_bar <= 'H1;
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DMA_bar <= 'H1;
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Rx_MWr_Tag <= 'H80;
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Rx_MWr_Tag <= 'H80;
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Rx_MRd_Tag <= 'H20;
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Rx_MRd_Tag <= 'H10;
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// Initialization: TLP
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// Initialization: TLP
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# 400
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# 400
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Rx_TLP_Length <= 'H01;
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Rx_TLP_Length <= 'H01;
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| Line 765... |
Line 763... |
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
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Rx_MWr_Tag <= Rx_MWr_Tag + 1;
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Gap_Insert_Rx;
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Gap_Insert_Rx;
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Gap_Insert_Rx;
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Gap_Insert_Rx;
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# `T_DELTA // Polling the DMA status
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Hdr_Array[0] <= `HEADER0_MRD3_ | Rx_TLP_Length[9:0];
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Hdr_Array[1] <= {`C_HOST_RDREQ_ID, 3'H3, Rx_MRd_Tag, 4'Hf, 4'Hf};
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Hdr_Array[2] <= `C_ADDR_DMA_DS_STA;
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# `T_DELTA
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TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
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Rx_MRd_Tag <= Rx_MRd_Tag + 1;
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Gap_Insert_Rx;
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FSM_Trn <= 'H18;
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FSM_Trn <= 'H18;
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// feeding the payload CplD
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// feeding the payload CplD
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wait (tx_MRd_come);
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wait (tx_MRd_come);
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| Line 822... |
Line 831... |
TLP_Feed_Rx(`USE_PUBLIC, CplD_Index, `C_NO_BAR_HIT);
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TLP_Feed_Rx(`USE_PUBLIC, CplD_Index, `C_NO_BAR_HIT);
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CplD_Index <= CplD_Index + Rx_TLP_Length;
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CplD_Index <= CplD_Index + Rx_TLP_Length;
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Gap_Insert_Rx;
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Gap_Insert_Rx;
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Rx_TLP_Length <= 'H01;
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# `T_DELTA // Polling the DMA status
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Hdr_Array[0] <= `HEADER0_MRD3_ | Rx_TLP_Length[9:0];
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Hdr_Array[1] <= {`C_HOST_RDREQ_ID, 3'H3, Rx_MRd_Tag, 4'Hf, 4'Hf};
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Hdr_Array[2] <= `C_ADDR_DMA_DS_STA;
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# `T_DELTA
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TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
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Rx_MRd_Tag <= Rx_MRd_Tag + 1;
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Gap_Insert_Rx;
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FSM_Trn <= 'H1C;
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FSM_Trn <= 'H1C;
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# `T_DMA_INTERVAL
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# `T_DMA_INTERVAL
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;
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;
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| Line 902... |
Line 924... |
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
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Rx_MWr_Tag <= Rx_MWr_Tag + 1;
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Gap_Insert_Rx;
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Gap_Insert_Rx;
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Gap_Insert_Rx;
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Gap_Insert_Rx;
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Rx_TLP_Length <= 'H01;
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# `T_DELTA // Polling the DMA status
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Hdr_Array[0] <= `HEADER0_MRD3_ | Rx_TLP_Length[9:0];
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Hdr_Array[1] <= {`C_HOST_RDREQ_ID, 3'H3, Rx_MRd_Tag, 4'Hf, 4'Hf};
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Hdr_Array[2] <= `C_ADDR_DMA_US_STA;
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# `T_DELTA
|
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TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
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Rx_MRd_Tag <= Rx_MRd_Tag + 1;
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Gap_Insert_Rx;
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FSM_Trn <= 'H20;
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FSM_Trn <= 'H20;
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# (`T_DMA_INTERVAL*4)
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# (`T_DMA_INTERVAL*4)
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;
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;
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| Line 1139... |
Line 1173... |
TLP_Feed_Rx(`USE_PUBLIC, CplD_Index, `C_NO_BAR_HIT);
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TLP_Feed_Rx(`USE_PUBLIC, CplD_Index, `C_NO_BAR_HIT);
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CplD_Index <= CplD_Index + Rx_TLP_Length;
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CplD_Index <= CplD_Index + Rx_TLP_Length;
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Gap_Insert_Rx;
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Gap_Insert_Rx;
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Rx_TLP_Length <= 'H01;
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# `T_DELTA // Polling the DMA status
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Hdr_Array[0] <= `HEADER0_MRD3_ | Rx_TLP_Length[9:0];
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Hdr_Array[1] <= {`C_HOST_RDREQ_ID, 3'H3, Rx_MRd_Tag, 4'Hf, 4'Hf};
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Hdr_Array[2] <= `C_ADDR_DMA_DS_STA;
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# `T_DELTA
|
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TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
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Rx_MRd_Tag <= Rx_MRd_Tag + 1;
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Gap_Insert_Rx;
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FSM_Trn <= 'H2C;
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FSM_Trn <= 'H2C;
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// feeding the payload CplD (2nd descriptor)
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// feeding the payload CplD (2nd descriptor)
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wait (tx_MRd_come);
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wait (tx_MRd_come);
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| Line 1304... |
Line 1351... |
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
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Rx_MWr_Tag <= Rx_MWr_Tag + 1;
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Gap_Insert_Rx;
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Gap_Insert_Rx;
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Gap_Insert_Rx;
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Gap_Insert_Rx;
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Rx_TLP_Length <= 'H01;
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# `T_DELTA // Polling the DMA status
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Hdr_Array[0] <= `HEADER0_MRD3_ | Rx_TLP_Length[9:0];
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Hdr_Array[1] <= {`C_HOST_RDREQ_ID, 3'H3, Rx_MRd_Tag, 4'Hf, 4'Hf};
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Hdr_Array[2] <= `C_ADDR_DMA_US_STA;
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# `T_DELTA
|
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TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
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Rx_MRd_Tag <= Rx_MRd_Tag + 1;
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Gap_Insert_Rx;
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|
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FSM_Trn <= 'H34;
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FSM_Trn <= 'H34;
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// feeding the descriptor CplD
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// feeding the descriptor CplD
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wait (Desc_tx_MRd_Valid);
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wait (Desc_tx_MRd_Valid);
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| Line 1340... |
Line 1399... |
# `T_DELTA
|
# `T_DELTA
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TLP_Feed_Rx(`USE_PRIVATE, 0, `C_NO_BAR_HIT);
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TLP_Feed_Rx(`USE_PRIVATE, 0, `C_NO_BAR_HIT);
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Gap_Insert_Rx;
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Gap_Insert_Rx;
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|
|
|
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Rx_TLP_Length <= 'H01;
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# `T_DELTA // Polling the DMA status
|
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Hdr_Array[0] <= `HEADER0_MRD3_ | Rx_TLP_Length[9:0];
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Hdr_Array[1] <= {`C_HOST_RDREQ_ID, 3'H3, Rx_MRd_Tag, 4'Hf, 4'Hf};
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Hdr_Array[2] <= `C_ADDR_DMA_US_STA;
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|
|
|
|
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# `T_DELTA
|
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TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
|
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Rx_MRd_Tag <= Rx_MRd_Tag + 1;
|
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Gap_Insert_Rx;
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|
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|
|
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# (`T_DMA_INTERVAL*4)
|
|
;
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|
|
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Rx_TLP_Length <= 'H01;
|
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# `T_DELTA // Polling the DMA status
|
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Hdr_Array[0] <= `HEADER0_MRD3_ | Rx_TLP_Length[9:0];
|
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Hdr_Array[1] <= {`C_HOST_RDREQ_ID, 3'H3, Rx_MRd_Tag, 4'Hf, 4'Hf};
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Hdr_Array[2] <= `C_ADDR_DMA_US_STA;
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|
|
|
|
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# `T_DELTA
|
|
TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
|
|
Rx_MRd_Tag <= Rx_MRd_Tag + 1;
|
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Gap_Insert_Rx;
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|
|
FSM_Trn <= 'H38;
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FSM_Trn <= 'H38;
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|
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# (`T_DMA_INTERVAL*8)
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# (`T_DMA_INTERVAL*4)
|
;
|
;
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|
|
|
|
//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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|
|
| Line 1688... |
Line 1774... |
Err_signal <= 0;
|
Err_signal <= 0;
|
FSM_TLP_Fmt <= 'H10;
|
FSM_TLP_Fmt <= 'H10;
|
end
|
end
|
else if (tx_TLP_is_CplD) begin
|
else if (tx_TLP_is_CplD) begin
|
Err_signal <= 1;
|
Err_signal <= 1;
|
$display ("\n %t:\n !! CplD Requester ID Wrong (TLP Length ==1 )!! ", $time);
|
$display ("\n %t:\n !! Tx CplD Requester ID Wrong (TLP Length ==1 )!! ", $time);
|
|
FSM_TLP_Fmt <= 'H10;
|
end
|
end
|
else begin
|
else begin
|
Err_signal <= 0;
|
Err_signal <= 0;
|
FSM_TLP_Fmt <= 'H10;
|
FSM_TLP_Fmt <= 'H10;
|
end
|
end
|
| Line 1708... |
Line 1795... |
tx_TLP_Length <= tx_TLP_Length - 1;
|
tx_TLP_Length <= tx_TLP_Length - 1;
|
FSM_TLP_Fmt <= 'H20;
|
FSM_TLP_Fmt <= 'H20;
|
end
|
end
|
else if (tx_TLP_is_CplD) begin
|
else if (tx_TLP_is_CplD) begin
|
Err_signal <= 1;
|
Err_signal <= 1;
|
$display ("\n %t:\n !! CplD Requester ID Wrong (TLP Length !=1 )!! ", $time);
|
$display ("\n %t:\n !! Tx CplD Requester ID Wrong (TLP Length !=1 )!! ", $time);
|
|
FSM_TLP_Fmt <= 'H20;
|
end
|
end
|
else begin
|
else begin
|
tx_TLP_Length <= tx_TLP_Length - 1;
|
tx_TLP_Length <= tx_TLP_Length - 1;
|
FSM_TLP_Fmt <= 'H20;
|
FSM_TLP_Fmt <= 'H20;
|
end
|
end
|
