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-- PDP-1C had full multiply and divide instructions of variable time.
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-- PDP-1C had full multiply and divide instructions of variable time.
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Why does isim behave like unsigned+natural doesn't exist?
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity pdp1cpu is
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entity pdp1cpu is
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Port (
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Port (
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AWAKE : out STD_LOGIC;
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AWAKE : out STD_LOGIC;
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-- user visible registers
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-- user visible registers
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AC : inout STD_LOGIC_VECTOR(0 to 17) := (others=>'0'); -- accumulator
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AC : inout STD_LOGIC_VECTOR(0 to 17) := (others=>'0'); -- accumulator
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IO : inout STD_LOGIC_VECTOR(0 to 17) := (others=>'0'); -- I/O
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IO : inout STD_LOGIC_VECTOR(0 to 17) := (others=>'0'); -- I/O
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PC : inout unsigned(0 to 11) := (others=>'0'); -- program counter
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PC : inout STD_LOGIC_VECTOR(0 to 11) := (others=>'0'); -- program counter
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PF : inout STD_LOGIC_VECTOR(1 to 6) := (others=>'0'); -- program flags
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PF : inout STD_LOGIC_VECTOR(1 to 6) := (others=>'0'); -- program flags
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OV : inout STD_LOGIC := '0'; -- overflow flag
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OV : inout STD_LOGIC := '0'; -- overflow flag
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-- user settable switches
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-- user settable switches
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SW_TESTA : in std_logic_vector(0 to 11) := (others => '0'); -- test address
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SW_TESTA : in std_logic_vector(0 to 11) := (others => '0'); -- test address
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MB <= M_DO;
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MB <= M_DO;
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case cycletype is
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case cycletype is
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when load_instruction => -- it's our next instruction
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when load_instruction => -- it's our next instruction
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op <= M_DO(0 to 5);
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op <= M_DO(0 to 5);
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if op/=op_xct then -- indirect execution
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if op/=op_xct then -- indirect execution
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PC<=PC+1;
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PC<=std_logic_vector(unsigned(PC)+1);
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end if;
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end if;
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when load_indirect => -- completing an indirect instruction
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when load_indirect => -- completing an indirect instruction
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ib <= M_DO(5); -- update indirection bit
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ib <= M_DO(5); -- update indirection bit
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when others => -- data access cycle
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when others => -- data access cycle
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end case;
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end case;
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if ((op=op_skip or op=op_skipi) and (skipcond xor ib)='1') or
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if ((op=op_skip or op=op_skipi) and (skipcond xor ib)='1') or
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(op=op_isp and cycletype=store_data and AC(0)='0') or
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(op=op_isp and cycletype=store_data and AC(0)='0') or
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(op=op_sas and cycletype=load_data and ac_eq_mb) or
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(op=op_sas and cycletype=load_data and ac_eq_mb) or
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(op=op_sad and cycletype=load_data and not ac_eq_mb) or
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(op=op_sad and cycletype=load_data and not ac_eq_mb) or
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FALSE then -- increase PC an extra time
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FALSE then -- increase PC an extra time
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PC <= PC+1;
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PC <= std_logic_vector(unsigned(PC)+1);
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end if;
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end if;
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if (op=op_skip or op=op_skipi) and szo='1' then
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if (op=op_skip or op=op_skipi) and szo='1' then
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OV <= '0'; -- clear overflow after checking it
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OV <= '0'; -- clear overflow after checking it
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end if;
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end if;
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when cycle_setup_read => -- set up the memory address
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when cycle_setup_read => -- set up the memory address
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if op=op_cal or op=op_jda then
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if op=op_cal or op=op_jda then
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if op=op_cal then
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if op=op_cal then
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PC <= o"0101";
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PC <= o"0101";
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MA <= o"0100";
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MA <= o"0100";
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else
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else
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PC <= unsigned(y)+1;
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PC <= std_logic_vector(unsigned(y)+1);
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MA <= y;
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MA <= y;
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end if;
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end if;
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cycletype <= store_data;
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cycletype <= store_data;
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else
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else
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MA <= y;
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MA <= y;
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PC <= unsigned(y);
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PC <= y;
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cycletype <= load_instruction;
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cycletype <= load_instruction;
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end if;
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end if;
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when op_skipi|op_rotshiftr|op_lawm|op_iot_nw =>
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when op_skipi|op_rotshiftr|op_lawm|op_iot_nw =>
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-- instructions with IB set, yet are immediate
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-- instructions with IB set, yet are immediate
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MA <= std_logic_vector(PC);
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MA <= std_logic_vector(PC);
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