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https://opencores.org/ocsvn/pit/pit/trunk
[/] [pit/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Diff between revs 3 and 8
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| Rev 3 |
Rev 8 |
| Line 53... |
Line 53... |
wire [31:0] adr;
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wire [31:0] adr;
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wire [15:0] dat_i, dat_o, dat0_i, dat1_i, dat2_i, dat3_i;
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wire [15:0] dat_i, dat_o, dat0_i, dat1_i, dat2_i, dat3_i;
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wire we;
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wire we;
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wire stb;
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wire stb;
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wire cyc;
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wire cyc;
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wire ack;
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wire ack, ack_1, ack_2, ack_3, ack_4;
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wire inta_1, inta_2, inta_3, inta_4;
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wire inta_1, inta_2, inta_3, inta_4;
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wire count_en_1;
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wire count_en_1;
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wire count_flag_1;
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wire count_flag_1;
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reg [15:0] q, qq;
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reg [15:0] q, qq;
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| Line 153... |
Line 153... |
assign dat_i = ({16{stb0}} & dat0_i) |
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assign dat_i = ({16{stb0}} & dat0_i) |
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({16{stb1}} & dat1_i) |
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({16{stb1}} & dat1_i) |
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({16{stb2}} & dat2_i) |
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({16{stb2}} & dat2_i) |
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({16{stb3}} & {8'b0, dat3_i[7:0]});
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({16{stb3}} & {8'b0, dat3_i[7:0]});
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assign ack = ack_1 || ack_2 || ack_3 || ack_4;
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// hookup wishbone_PIT_master core - Parameters take all default values
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// hookup wishbone_PIT_master core - Parameters take all default values
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// Async Reset, 16 bit Bus, 16 bit Granularity
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// Async Reset, 16 bit Bus, 16 bit Granularity
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pit_top pit_1(
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pit_top pit_1(
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// wishbone interface
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// wishbone interface
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.wb_clk_i(mstr_test_clk),
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.wb_clk_i(mstr_test_clk),
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| Line 167... |
Line 169... |
.wb_dat_o(dat0_i),
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.wb_dat_o(dat0_i),
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.wb_we_i(we),
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.wb_we_i(we),
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.wb_stb_i(stb0),
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.wb_stb_i(stb0),
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.wb_cyc_i(cyc),
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.wb_cyc_i(cyc),
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.wb_sel_i( 2'b11 ),
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.wb_sel_i( 2'b11 ),
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.wb_ack_o(ack),
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.wb_ack_o(ack_1),
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.pit_irq_o(inta_1),
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.pit_irq_o(inta_1),
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.pit_o(pit_1_out),
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.pit_o(pit_1_out),
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.ext_sync_i(1'b0),
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.ext_sync_i(1'b0),
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.cnt_sync_o(count_en_1),
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.cnt_sync_o(count_en_1),
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| Line 191... |
Line 193... |
.wb_dat_o(dat1_i),
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.wb_dat_o(dat1_i),
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.wb_we_i(we),
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.wb_we_i(we),
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.wb_stb_i(stb1),
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.wb_stb_i(stb1),
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.wb_cyc_i(cyc),
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.wb_cyc_i(cyc),
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.wb_sel_i( 2'b11 ),
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.wb_sel_i( 2'b11 ),
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.wb_ack_o(ack),
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.wb_ack_o(ack_2),
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.pit_irq_o(inta_2),
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.pit_irq_o(inta_2),
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.pit_o(pit_2_out),
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.pit_o(pit_2_out),
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.ext_sync_i(count_en_1),
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.ext_sync_i(count_en_1),
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.cnt_sync_o(count_en_2),
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.cnt_sync_o(count_en_2),
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| Line 215... |
Line 217... |
.wb_dat_o(dat2_i),
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.wb_dat_o(dat2_i),
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.wb_we_i(we),
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.wb_we_i(we),
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.wb_stb_i(stb2),
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.wb_stb_i(stb2),
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.wb_cyc_i(cyc),
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.wb_cyc_i(cyc),
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.wb_sel_i( 2'b11 ),
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.wb_sel_i( 2'b11 ),
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.wb_ack_o(ack),
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.wb_ack_o(ack_3),
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.pit_irq_o(inta_3),
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.pit_irq_o(inta_3),
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.pit_o(pit_3_out),
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.pit_o(pit_3_out),
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.ext_sync_i(count_en_1),
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.ext_sync_i(count_en_1),
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.cnt_sync_o(count_en_3),
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.cnt_sync_o(count_en_3),
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| Line 239... |
Line 241... |
.wb_dat_o(dat3_i[7:0]),
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.wb_dat_o(dat3_i[7:0]),
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.wb_we_i(we),
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.wb_we_i(we),
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.wb_stb_i(stb3),
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.wb_stb_i(stb3),
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.wb_cyc_i(cyc),
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.wb_cyc_i(cyc),
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.wb_sel_i( 2'b11 ),
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.wb_sel_i( 2'b11 ),
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.wb_ack_o(ack),
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.wb_ack_o(ack_4),
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.pit_irq_o(inta_4),
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.pit_irq_o(inta_4),
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.pit_o(pit_4_out),
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.pit_o(pit_4_out),
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.ext_sync_i(count_en_1),
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.ext_sync_i(count_en_1),
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.cnt_sync_o(count_en_4),
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.cnt_sync_o(count_en_4),
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