| Line 39... |
Line 39... |
module pit_top #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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module pit_top #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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parameter PRE_COUNT_SIZE = 15, // Prescale Counter size
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parameter PRE_COUNT_SIZE = 15, // Prescale Counter size
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parameter COUNT_SIZE = 16, // Main counter size
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parameter COUNT_SIZE = 16, // Main counter size
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parameter DECADE_CNTR = 1'b1, // Prescale rollover decode
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parameter DECADE_CNTR = 1'b1, // Prescale rollover decode
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parameter NO_PRESCALE = 1'b0, // Remove prescale function
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parameter NO_PRESCALE = 1'b0, // Remove prescale function
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parameter SINGLE_CYCLE = 1'b0, // No bus wait state added
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parameter DWIDTH = 16) // Data bus width
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parameter DWIDTH = 16) // Data bus width
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(
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(
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// Wishbone Signals
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// Wishbone Signals
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output [DWIDTH-1:0] wb_dat_o, // databus output
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output [DWIDTH-1:0] wb_dat_o, // databus output
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output wb_ack_o, // bus cycle acknowledge output
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output wb_ack_o, // bus cycle acknowledge output
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wire [ 3:0] pit_pre_scl; // Prescaler modulo
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wire [ 3:0] pit_pre_scl; // Prescaler modulo
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wire counter_sync; //
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wire counter_sync; //
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// Wishbone Bus interface
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// Wishbone Bus interface
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pit_wb_bus #(.ARST_LVL(ARST_LVL),
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pit_wb_bus #(.ARST_LVL(ARST_LVL),
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.SINGLE_CYCLE(SINGLE_CYCLE),
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.DWIDTH(DWIDTH))
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.DWIDTH(DWIDTH))
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wishbone(
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wishbone(
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.wb_dat_o ( wb_dat_o ),
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.wb_dat_o ( wb_dat_o ),
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.wb_ack_o ( wb_ack_o ),
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.wb_ack_o ( wb_ack_o ),
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.wb_clk_i ( wb_clk_i ),
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.wb_clk_i ( wb_clk_i ),
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