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Line 106... |
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// WISHBONE Read Data Mux
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// WISHBONE Read Data Mux
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always @*
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always @*
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case ({eight_bit_bus, wb_adr_i}) // synopsys parallel_case
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case ({eight_bit_bus, wb_adr_i}) // synopsys parallel_case
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// 8 bit Bus, 8 bit Granularity
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// 8 bit Bus, 8 bit Granularity
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4'b1_000: rd_data_mux <= read_regs[ 7: 0]; // 8 bit read address 0
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4'b1_000: rd_data_mux = read_regs[ 7: 0]; // 8 bit read address 0
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4'b1_001: rd_data_mux <= read_regs[15: 8]; // 8 bit read address 1
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4'b1_001: rd_data_mux = read_regs[15: 8]; // 8 bit read address 1
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4'b1_010: rd_data_mux <= read_regs[23:16]; // 8 bit read address 2
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4'b1_010: rd_data_mux = read_regs[23:16]; // 8 bit read address 2
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4'b1_011: rd_data_mux <= read_regs[31:24]; // 8 bit read address 3
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4'b1_011: rd_data_mux = read_regs[31:24]; // 8 bit read address 3
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4'b1_100: rd_data_mux <= read_regs[39:32]; // 8 bit read address 4
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4'b1_100: rd_data_mux = read_regs[39:32]; // 8 bit read address 4
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4'b1_101: rd_data_mux <= read_regs[47:40]; // 8 bit read address 5
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4'b1_101: rd_data_mux = read_regs[47:40]; // 8 bit read address 5
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// 16 bit Bus, 16 bit Granularity
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// 16 bit Bus, 16 bit Granularity
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4'b0_000: rd_data_mux <= read_regs[15: 0]; // 16 bit read access address 0
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4'b0_000: rd_data_mux = read_regs[15: 0]; // 16 bit read access address 0
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4'b0_001: rd_data_mux <= read_regs[31:16];
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4'b0_001: rd_data_mux = read_regs[31:16];
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4'b0_010: rd_data_mux <= read_regs[47:32];
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4'b0_010: rd_data_mux = read_regs[47:32];
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endcase
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endcase
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// generate wishbone write register strobes -- one hot if 8 bit bus
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// generate wishbone write register strobes -- one hot if 8 bit bus
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always @*
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always @*
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begin
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begin
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