URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] [pit/] [trunk/] [rtl/] [verilog/] [pit_wb_bus.v] - Diff between revs 2 and 9

Rev 2	Rev 9
Line 74...	Line 74...

`assign async_rst_b = arst_i ^ ARST_LVL;`	`assign async_rst_b = arst_i ^ ARST_LVL;`
`assign sync_reset = wb_rst_i;`	`assign sync_reset = wb_rst_i;`

`// generate wishbone signals`	`// generate wishbone signals`
`wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;`	`wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i & wb_ack_o;`

`// generate acknowledge output signal`	`// generate acknowledge output signal`
`always @(posedge wb_clk_i)`	`always @(posedge wb_clk_i)`
`wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored`	`wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored`