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% Document variables
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% Document variables
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\docDate{ \today }
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\docDate{ \today }
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\docID{Present Decoder}
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\docID{Present Decoder}
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\docRevision{0.1}
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\docRevision{0.2}
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\docStatus{Draft}
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\docStatus{Draft}
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\docTitle{\mbox{Present Decoder}}
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\docTitle{\mbox{Present Decoder}}
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\authorName{\mbox{Krzysztof Gajewski} \\ and opencores.org}
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\authorName{\mbox{Krzysztof Gajewski} \\ and opencores.org}
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\authorURL{www.opencores.org}
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\authorURL{www.opencores.org}
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\authorAddress{\mbox{}}
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\authorAddress{\mbox{}}
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\authorEmail{gajos@opencores.org}
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\authorEmail{gajos@opencores.org}
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\revisionList{
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\revisionList{
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0.1 & all & 2014/05/25 & First draft & K. Gajewski \\
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0.1 & all & 2014/05/25 & First draft & K. Gajewski \\
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0.2 & all & 2014/09/16 & Some small corrections with the text, typos, etc. & K. Gajewski \\
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}
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}
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\begin{document}
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\begin{document}
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\maketitle
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\maketitle
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Briefly block scheme of the PRESENT block cipher
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Briefly block scheme of the PRESENT block cipher
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}%
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}%
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\label{pAlgorithm}
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\label{pAlgorithm}
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\end{center}
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\end{center}
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\end{figure}
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\end{figure}
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In subprojects \texttt{Pure} and \texttt{PureTesting} Present coder components was presented. In this project Present decoder was presented. Decoding key is firstly generated, basing on the key used for data coding. Next, input data are decoded (taking into account "inverse" direction to the presented in Fig. \ref{pAlgorithm}), and at last feeds the output. This core works with 80 bit key. Target was Xilinx\textsuperscript{\textregistered} Spartan 3E XC3S500E \cite{Spartan} on Spartan 3E Starter Board \cite{Digilent} made by Digilent\textsuperscript{\textregistered}.
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In subprojects \texttt{Pure} and \texttt{PureTesting} Present encoder components was presented. In this subproject Present decoder was presented. Decoding key is firstly generated, basing on the key used for data coding. Next, input data are decoded (taking into account "inverse" direction to the presented in Fig. \ref{pAlgorithm}), and at last feeds the output. This core works with 80 bit key. Target was Xilinx\textsuperscript{\textregistered} Spartan 3E XC3S500E \cite{Spartan} on Spartan 3E Starter Board \cite{Digilent} made by Digilent\textsuperscript{\textregistered}.
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\newpage
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\newpage
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\section{Interface}
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\section{Interface}
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Top level component of Present decoder was shown in Fig. \ref{pfdec}. All inputs and outputs are synchronous except \texttt{reset} signal and sampled at rising edge of the clock. Type for all signals is \texttt{STD\_LOGIC} or \texttt{STD\_LOGIC\_VECTOR}.
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Top level component of the Present decoder was shown in Fig. \ref{pfdec}. All inputs and outputs are synchronous except \texttt{reset} signal and sampled at rising edge of the clock. Type for all signals is \texttt{STD\_LOGIC} or \texttt{STD\_LOGIC\_VECTOR}.
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\begin{figure}[!ht]%
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\begin{figure}[!ht]%
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\begin{center}
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\begin{center}
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\includegraphics[width=0.5\textwidth]{img/PresentFullDecoder.png}
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\includegraphics[width=0.5\textwidth]{img/PresentFullDecoder.png}
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\caption{%
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\caption{%
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Top level component of Present decoder
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Top level component of the Present decoder
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}%
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}%
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\label{pfdec}
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\label{pfdec}
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\end{center}
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\end{center}
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\end{figure}
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\end{figure}
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\begin{tabularx}{\textwidth}{|p{30mm}|p{11mm}|p{11mm}|X|}
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\begin{tabularx}{\textwidth}{|p{30mm}|p{11mm}|p{11mm}|X|}
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\hline \bf{Signal name} & \bf{Width} & \bf{In/Out} & \bf{Description}\\
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\hline \bf{Signal name} & \bf{Width} & \bf{In/Out} & \bf{Description}\\
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\hline \texttt{ciphertext} & 64 & in & input data which have to be decoded. \\
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\hline \texttt{ciphertext} & 64 & in & input data which have to be decoded. \\
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\hline \texttt{key} & 80 & in & secret key used for input data decoding (the same which was used for data encoding). \\
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\hline \texttt{key} & 80 & in & secret key used for input data decoding (the same which was used for data encoding). \\
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\hline \texttt{clk} & 1 & in & clock signal for the component\\
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\hline \texttt{clk} & 1 & in & clock signal for the component\\
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\hline \texttt{reset} & 1 & in & \emph{Asynchronous} reset signal. \\
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\hline \texttt{reset} & 1 & in & \emph{asynchronous} reset signal. \\
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\hline \texttt{start} & 1 & in & signal which starts decoding process. \\
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\hline \texttt{start} & 1 & in & signal which starts decoding process. \\
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\hline \texttt{plaintext} & 64 & out & decoded text output. \\
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\hline \texttt{plaintext} & 64 & out & decoded text output. \\
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\hline \texttt{ready} & 1 & out & signal informing about end of decoding process. \newline "0" - wait until end of data decoding. \newline "1" - data at the \texttt{ciphertext} output are valid, you can read them. \\
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\hline \texttt{ready} & 1 & out & signal informing about end of decoding process. \newline "0" - wait until end of data decoding. \newline "1" - data at the \texttt{ciphertext} output are valid, you can read them. \\
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\hline
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\hline
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\end{tabularx}
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\end{tabularx}
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\captionof{table}{Input/Output signals of Present Decoder component}
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\captionof{table}{Input/Output signals of the Present Decoder component}
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\newpage
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\newpage
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\section{Internal structure and state machine workflow}
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\section{Internal structure and state machine workflow}
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\begin{figure}[!ht]%
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\begin{figure}[!ht]%
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\begin{center}
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\begin{center}
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\includegraphics[width=0.8\textwidth]{img/internalStructure.png}
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\includegraphics[width=0.8\textwidth]{img/internalStructure.png}
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\caption{%
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\caption{%
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Internal datapath between main components in Present decoder.
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Internal datapath between main components in the Present decoder.
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}%
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}%
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\label{internalStructure}
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\label{internalStructure}
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\end{center}
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\end{center}
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\end{figure}
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\end{figure}
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}%
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}%
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\label{presentDecSM}
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\label{presentDecSM}
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\end{center}
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\end{center}
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\end{figure}
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\end{figure}
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State machine of the \texttt{PresentDec} component was shown in Fig. \ref{presentDecSM}. It consist of three states \texttt{NOP}, \texttt{SM\_START} and \texttt{READY}. The way of work of this state machine is the same as in the \texttt{Present} subproject, but the counter is counting down instead of counting up.
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State machine of the \texttt{PresentDec} component was shown in Fig. \ref{presentDecSM}. It consists of three states \texttt{NOP}, \texttt{SM\_START} and \texttt{READY}. The way of work of this state machine is the same as in the \texttt{Present} subproject, but the counter is counting down instead of counting up.
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\begin{figure}[!ht]%
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\begin{figure}[!ht]%
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\begin{center}
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\begin{center}
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\includegraphics[width=0.5\textwidth]{img/FullDecoderSM.jpg}
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\includegraphics[width=0.5\textwidth]{img/FullDecoderSM.jpg}
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\caption{%
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\caption{%
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}%
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}%
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\label{presentFullDecSM}
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\label{presentFullDecSM}
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\end{center}
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\end{center}
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\end{figure}
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\end{figure}
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State machine of the \texttt{FullDecoderSM} component was shown in Fig. \ref{presentFullDecSM}. It consist of four states \texttt{NOP}, \texttt{KG\_START}, \texttt{DEC\_START} and \texttt{READY}. \texttt{NOP} is default state after resetting the core. This state is active as long as \texttt{full\_decoder\_start} = '0'.
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State machine of the \texttt{FullDecoderSM} component was shown in Fig. \ref{presentFullDecSM}. It consists of four states \texttt{NOP}, \texttt{KG\_START}, \texttt{DEC\_START} and \texttt{READY}. \texttt{NOP} is the default state after resetting the core. This state is active as long as \texttt{full\_decoder\_start} = '0'.
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When \texttt{full\_decoder\_start} = '1' key generation for the decoding process starts. Proper \texttt{key} and \texttt{ciphertext} must feed the input before. \texttt{KG\_START} state is active as long \texttt{PresentEncKeyGen} is generating the key. Key generation ends, when \texttt{PresentEncKeyGen} sets the \texttt{ready} signal to '1'. When the \texttt{ready} signal is set to '1', the state is changing.
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When \texttt{full\_decoder\_start} = '1' key generation for the decoding process starts. Proper \texttt{key} and \texttt{ciphertext} must feed the input before. \texttt{KG\_START} state is active as long \texttt{PresentEncKeyGen} is generating the key. Key generation ends, when \texttt{PresentEncKeyGen} sets the \texttt{ready} signal to '1'. When the \texttt{ready} signal is set to '1', the state is changing.
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During \texttt{DEC\_START} state decoding process appears. State machine is in this state until \texttt{PresentDec} ends its works. The end of decoding is signalled by setting the \texttt{ready} signal to '1' by the \texttt{PresentDec} component. Then, the state is changing.
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During \texttt{DEC\_START} state decoding process appears. State machine is in this state until \texttt{PresentDec} ends its works. The end of decoding is signalled by setting the \texttt{ready} signal to '1' by the \texttt{PresentDec} component. Then, the state is changing.
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\texttt{READY} sets the \texttt{ready} signal of the \texttt{PresentFullDecoder} to '1'. It is idle-like state, when the user can reads the output of the Present decoder. The state machine is in this state until the user sets the \texttt{full\_decoder\_start} to '0'.
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\texttt{READY} state sets the \texttt{ready} signal of the \texttt{PresentFullDecoder} to '1'. It is idle-like state, when user can read the output of the Present decoder. The state machine is in this state until user sets the \texttt{full\_decoder\_start} to '0'.
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\newpage
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\newpage
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\section{FPGA implementations}
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\section{FPGA implementations}
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\captionof{table}{Synthesis results for Spartan 3E XC3S500E}
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\captionof{table}{Synthesis results for Spartan 3E XC3S500E}
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Possible change in used FPGA device may be possible in steps given below\footnotemark[1]:
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Possible change in used FPGA device may be possible in steps given below\footnotemark[1]:
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\begin{enumerate}
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\begin{enumerate}
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\item Copy \texttt{./Decode/syn/XC3ES500/} directory to another one like \texttt{./Decode/syn/YOUR\_FPGA\_SYMBOL/}
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\item Copy \texttt{./Decode/syn/XC3ES500/} directory to another one like \texttt{./Decode/syn/YOUR\_FPGA\_SYMBOL/}
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\item Go to \texttt{./Decode/syn/XC3ES500/} directory.
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\item Go to \texttt{./Decode/syn/YOUR\_FPGA\_SYMBOL/} directory.
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\item In \texttt{PresentEnc.xst} file modify the line \texttt{-p xc3s500e-5-fg320} to \texttt{-p YOUR\_FPGA\_SYMBOL}
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\item In \texttt{PresentFullDecoder.xst} file modify the line \texttt{-p xc3s500e-5-fg320} to \texttt{-p YOUR\_FPGA\_CODE}
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\item In \texttt{Makefile} file modify the line \texttt{PLATFORM=xc3s500e-fg320-5} to \texttt{PLATFORM=YOUR\_FPGA\_SYMBOL}
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\item In \texttt{Makefile} file modify the line \texttt{PLATFORM=xc3s500e-fg320-5} to \texttt{PLATFORM=YOUR\_FPGA\_CODE}
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\end{enumerate}
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\end{enumerate}
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\footnotetext[1]{This solution was not tested and is based on my own observations. Additional care should be taken with *.UCF files. You can make this modifications on your own risk}
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\footnotetext[1]{This solution was not tested and is based on my own observations.}
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\newpage
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\newpage
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\section{Simulation}
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\section{Simulation}
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Self-checking test bench were provided to the components used for Present encoder. They are stored in \texttt{./Decode/bench/vhdl} directory. Suitable configuration files and Makefile used for running test bench was stored in
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Self-checking test bench were provided to the components used for the Present encoder. They are stored in \texttt{./Decode/bench/vhdl} directory. Suitable configuration files and Makefile used for running test bench was stored in
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\texttt{./Decode/sim/rtl\_sim/bin} directory. Appropriate test vectors was taken from \cite{PRESENT}.
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\texttt{./Decode/sim/rtl\_sim/bin} directory. Appropriate test vectors was taken from \cite{PRESENT}.
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Makefile was prepared to make "manual run" of tests. If You want to perform it without gui, remove \texttt{-gui} option in Makefaile.
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Makefile was prepared to make "manual run" of tests. If You want to perform it without gui, remove \texttt{-gui} option in Makefaile.
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\newpage
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\newpage
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