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[/] [present/] [trunk/] [DecodeTesting/] [bench/] [vhdl/] [ShiftRegTB.vhd] - Diff between revs 4 and 7

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Rev 4 Rev 7
Line 40... Line 40... 
---- from http://www.opencores.org/lgpl.shtml                      ----
 
---- from http://www.opencores.org/lgpl.shtml                      ----
 
----                                                               ----
 
----                                                               ----
 
-----------------------------------------------------------------------
 
-----------------------------------------------------------------------
 
LIBRARY ieee;
 
LIBRARY ieee;
 
USE ieee.std_logic_1164.ALL;
 
USE ieee.std_logic_1164.ALL;
 
use work.RSAFinalizerProperties.ALL;
 
 
 
 
 
 
 
-- Uncomment the following library declaration if using
 
-- Uncomment the following library declaration if using
 
-- arithmetic functions with Signed or Unsigned values
 
-- arithmetic functions with Signed or Unsigned values
 
--USE ieee.numeric_std.ALL;
 
--USE ieee.numeric_std.ALL;
 
 
 
 
Line 57... Line 56... 
 
 
 
 
    COMPONENT ShiftReg
 
    COMPONENT ShiftReg
 
--       generic (length_1      : integer :=  WORD_LENGTH;
 
--       generic (length_1      : integer :=  WORD_LENGTH;
 
--                length_2      : integer :=  BYTE
 
--                length_2      : integer :=  BYTE
 
         GENERIC (
 
         GENERIC (
 
             length_1      : integer :=  BYTE;
 
             length_1      : integer :=  8;
 
             length_2      : integer :=  WORD_LENGTH
 
             length_2      : integer :=  64
 
         );
 
         );
 
    PORT(
 
    PORT(
 
        input  : in  STD_LOGIC_VECTOR(7 downto 0);
 
        input  : in  STD_LOGIC_VECTOR(7 downto 0);
 
                  --input : IN  std_logic_vector(63 downto 0);
 
                  --input : IN  std_logic_vector(63 downto 0);
 
        output : out STD_LOGIC_VECTOR(63 downto 0);
 
        output : out STD_LOGIC_VECTOR(63 downto 0);
Line 120... Line 119... 
                input <= "10101010";
 
                input <= "10101010";
 
                --input <= "1111000011110000111100001111000011110000111100001111000011110000";
 
                --input <= "1111000011110000111100001111000011110000111100001111000011110000";
 
      wait for 100 ns;
 
      wait for 100 ns;
 
                reset <= '1';
 
                reset <= '1';
 
      wait for clk_period*10;
 
      wait for clk_period*10;
 
 
 
                reset <= '0';
 
                en <= '1';
 
                en <= '1';
 
                wait for clk_period*1;
 
                wait for clk_period*1;
 
                en <= '0';
 
                en <= '0';
 
                wait for clk_period*1;
 
                wait for clk_period*1;
 
                shift <= '1';
 
                shift <= '1';

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