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-----------------------------------------------------------------------
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---- ----
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---- Present - a lightweight block cipher project ----
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---- ----
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---- This file is part of the Present - a lightweight block ----
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---- cipher project ----
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---- http://www.http://opencores.org/project,present ----
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---- ----
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---- Description: ----
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---- Shift register with parallel input/output. Nothing special----
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---- except configuration - it enables wider input than output and ----
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---- inverse config. ----
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---- To Do: ----
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---- ----
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---- Author(s): ----
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---- - Krzysztof Gajewski, gajos@opencores.org ----
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---- k.gajewski@gmail.com ----
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---- ----
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-----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and-or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ShiftReg is
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generic (
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length_1 : integer := 8;
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length_2 : integer := 64;
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internal_data : integer := 64
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);
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port (
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input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0);
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output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0);
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en : in STD_LOGIC;
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shift : in STD_LOGIC;
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clk : in STD_LOGIC;
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reset : in STD_LOGIC
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);
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end ShiftReg;
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architecture Behavioral of ShiftReg is
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signal data : STD_LOGIC_VECTOR(internal_data - 1 downto 0);
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begin
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reg : process (clk, reset, data)
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begin
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if (clk'event and clk = '1') then
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if (reset = '1') then
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data <= (others => '0');
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elsif (en = '1') then
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data(internal_data - 1 downto internal_data - length_1) <= input;
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else
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if (shift = '1') then
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data <= '0' & data(internal_data - 1 downto 1);
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end if;
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end if;
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end if;
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output <= data(length_2 - 1 downto 0);
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end process reg;
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end Behavioral;
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