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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_SetTargetRegister.v] - Diff between revs 44 and 45
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| Rev 44 |
Rev 45 |
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Line 26... |
//=============================================================================
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//=============================================================================
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`define EX_IRQ 9'd449 // interrupt
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`define EX_IRQ 9'd449 // interrupt
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`define EX_NMI 9'd510 // non-maskable interrupt
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`define EX_NMI 9'd510 // non-maskable interrupt
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module Raptor64_SetTargetRegister(rst,clk,advanceR,advanceX,dIR,dAXC,xRt);
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module Raptor64_SetTargetRegister(rst,clk,advanceR,advanceX,dIR,dIRvalid,dAXC,xRt);
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input rst;
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input rst;
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input clk;
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input clk;
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input advanceR;
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input advanceR;
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input advanceX;
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input advanceX;
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input [31:0] dIR;
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input [31:0] dIR;
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input dIRvalid;
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input [3:0] dAXC;
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input [3:0] dAXC;
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output [8:0] xRt;
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output [8:0] xRt;
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reg [8:0] xRt;
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reg [8:0] xRt;
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wire [6:0] dOpcode = dIR[31:25];
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wire [6:0] dOpcode = dIR[31:25];
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Line 46... |
if (rst) begin
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if (rst) begin
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xRt <= 9'd0;
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xRt <= 9'd0;
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end
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end
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else begin
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else begin
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if (advanceR) begin
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if (advanceR) begin
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if (dIRvalid) begin
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casex(dOpcode)
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casex(dOpcode)
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`MISC:
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`MISC:
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case(dFunc)
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case(dFunc)
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`SYSCALL: xRt <= 9'd0;
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`SYSCALL: xRt <= 9'd0;
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default: xRt <= 9'd0;
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default: xRt <= 9'd0;
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`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
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`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
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xRt <= 9'd0;
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xRt <= 9'd0;
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default: xRt <= {dAXC,dIR[19:15]};
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default: xRt <= {dAXC,dIR[19:15]};
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endcase
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endcase
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end
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end
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else
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xRt <= 9'd0;
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end
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else if (advanceX)
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else if (advanceX)
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xRt <= 9'd0;
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xRt <= 9'd0;
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end
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end
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endmodule
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endmodule
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